STMicroelectronics STM32F405 - Page 1693

DocID018909 Rev 11 1693/1731
RM0090 Debug support (DBG)
1701
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DBG_CAN2_STOP DBG_CAN1_STOP
Reserved
DBG_I2C3_SMBUS_TIMEOUT DBG_I2C2_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT
Reserved
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1514131211109876543210
Reserved
DBG_IWDG_STOP
DBG_WWDG_STOP
DBG_RTC_STOP
Reserved
DBG_TIM14_STOP DBG_TIM13_STOP DBG_TIM12_STOP
DBG_TIM7_STOP DBG_TIM6_STOP DBG_TIM5_STOP DBG_TIM4_STOP DBG_TIM3_STOP DBG_TIM2_STOP
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Bits 31:27 Reserved, must be kept at reset value.
Bit 26 DBG_CAN2_STOP: Debug CAN2 stopped when Core is halted
0: Same behavior as in normal mode
1: The CAN2 receive registers are frozen
Bit 25 DBG_CAN1_STOP: Debug CAN2 stopped when Core is halted
0: Same behavior as in normal mode
1: The CAN2 receive registers are frozen
Bit 24 Reserved, must be kept at reset value.
Bit 23 DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted