STMicroelectronics STM32F405 - Page 1711

DocID018909 Rev 11 1711/1731
RM0090 Revision history
1726
19-Feb-2013 4
Updated Section 2: Memory and bus architecture.
Updated Figure 1: System architecture for STM32F405xx/07xx and
STM32F415xx/17xx devices, and Figure 1: System architecture for
STM32F405xx/07xx and STM32F415xx/17xx devices. Updated
Table 4: Memory mapping vs. Boot mode/physical remap. Updated
Figure 5: Sequential 32-bit instruction execution. removed note 1
from Table 12: Program/erase parallelism.
PWR:
Updated Figure 7: Power supply overview.
Updated Section 5.1.3: Voltage regulator.
Added ADCDC1 bit in Section 5.5.1: PWR power control register
(PWR_CR) for STM32F42xxx and STM32F43xxx.
SYSCFG:
Added ADCxDC2 bit in Section 8.2.3: SYSCFG peripheral mode
configuration register (SYSCFG_PMC) for STM32F42xxx and
STM32F43xxx.
ADC:
Updated Section 13.9.3: Interleaved mode, Section 13.9.4: Alternate
trigger mode, and Section 13.9.5: Combined regular/injected
simultaneous mode to describe case of interrupted conversion.
Updated Section : Temperature sensor, VREFINT and VBAT internal
channels, Section 13.10: Temperature sensor, and Section 13.11:
Battery charge monitoring.
RTC:
Updated BKP[31:0] bit description in Section 26.6.20: RTC backup
registers (RTC_BKPxR).
I2C:
Updated Section 27.3.5: Programmable noise filter.
Table 310. Document revision history (continued)
Date Version Changes