LCD-TFT Controller (LTDC) RM0090
494/1731 DocID018909 Rev 11
Bit 31 HSPOL: Horizontal Synchronization Polarity
This bit is set and cleared by software.
0: Horizontal Synchronization polarity is active low
1: Horizontal Synchronization polarity is active high
Bit 30 VSPOL: Vertical Synchronization Polarity
This bit is set and cleared by software.
0: Vertical Synchronization is active low
1: Vertical Synchronization is active high
Bit 29 DEPOL: Data Enable Polarity
This bit is set and cleared by software.
0: Data Enable polarity is active low
1: Data Enable polarity is active high
Bit 28 PCPOL: Pixel Clock Polarity
This bit is set and cleared by software.
0: input pixel clock
1: inverted input pixel clock
Bits 27:17 Reserved, must be kept at reset value
Bit 16 DEN: Dither Enable
This bit is set and cleared by software.
0: Dither disable
1: Dither enable
Bit 15 Reserved, must be kept at reset value
Bits 14:12 DRW[2:0]: Dither Red Width
These bits return the Dither Red Bits
Bit 11 Reserved, must be kept at reset value
Bits 10:8 DGW[2:0]: Dither Green Width
These bits return the Dither Green Bits
Bit 7 Reserved, must be kept at reset value
Bits 6:4 DBW[2:0]: Dither Blue Width
These bits return the Dither Blue Bits
Bits 3:1 Reserved, must be kept at reset value
Bit 0 LTDCEN: LCD-TFT controller enable bit
This bit is set and cleared by software.
0: LTDC disable
1: LTDC enable
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