EasyManuals Logo

Texas Instruments TMS320C6455 User Manual

Texas Instruments TMS320C6455
257 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #37 background imageLoading...
Page #37 background image
TMS320C6455
www.ti.com
SPRS276M MAY 2005REVISED MARCH 2012
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE
(1)
IPD/IPU
(2)
DESCRIPTION
NAME NO.
UXDATA7/MTXD7 N5
UXDATA6/MTXD6 M3 UTOPIA 8-bit transmit data bus (I/O/Z) [default] or EMAC MII 4-bit transmit data
bus (I/O/Z) [default] or EMAC GMII 8-bit transmit data bus or EMAC RMII 2-bit
UXDATA5/MTXD5 L5
transmit data bus (I/O/Z)
UXDATA4/MTXD4 L3
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the
UXDATA3/MTXD3 K4
O/Z UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.
UXDATA2/MTXD2 M4
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
UXDATA1/MTXD1/ pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
L4
RMTXD1 pins) to select the MII, RMII, GMII or RGMII EMAC interface. (For more details,
see Section 3, Device Configuration).
UXDATA0/MTXD0/
M1
RMTXD0
UTOPIA SLAVE (ATM CONTROLLER) - RECEIVE INTERFACE
Source clock for UTOPIA receive driven by Master ATM Controller.
URCLK/MRCLK H1 I/O/Z When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive clock. MACSEL[1:0] dependent.
Receive cell available status output signal from UTOPIA Slave.
0 indicates NO space is available to receive a cell from Master ATM Controller
URCLAV/MCRS/ 1 indicates space is available to receive a cell from Master ATM Controller
J4 I/O/Z
RMCRSDV When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII carrier sense [default] or RMII carrier sense/data valid or GMII
carrier sense. MACSEL[1:0] dependent. MACSEL[1:0] dependent.
UTOPIA receive interface enable input signal. Asserted by the Master ATM
Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus
URENB/MRXDV H5 I/O/Z (URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive data valid. MACSEL[1:0] dependent.
Receive Start-of-Cell signal. This signal is output by the Master ATM Controller
to indicate to the UTOPIA Slave that the first valid byte of the cell is available to
URSOC/MRXER/ sample on the 8-bit Receive Data Bus (URDATA[7:0]).
H4 I/O/Z
RMRXER When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or RMII or GMII receive error. MACSEL[1:0]
dependent.
URADDR4/PCBE0/ UTOPIA receive address pins [URADDR[4:0] (I)]:
P1 I
GP[2] As UTOPIA receive address pins, UTOPIA_EN (AEA12 pin) = 1:
5-bit Slave receive address input pins driven by the Master ATM Controller
URADDR3/PREQ/
P2 I
to identify and select one of the Slave devices (up to 31 possible) in the
GP[15]
ATM System.
URADDR2/PINTA
(1)
/
P3 I
When the UTOPIA peripheral is disabled [UTOPIA_EN (AEA12 pin) = 0],
GP[14]
these pins are PCI (if PCI_EN = 1) or GPIO (if PCI_EN = 0) pins
URADDR1/PRST/
(GP[15:12, 2]).
R5 I
GP[13]
As PCI peripheral pins:
PCI command/byte enable 0 (PCBE0) [I/O/Z]
PCI bus request (PREQ) [O/Z],
URADDR0/PGNT/
R4 I
PCI interrupt A (PINTA) [O/Z],
GP[12]
PCI reset (PRST) [I], and
PCI bus grant (PGNT) [I/O/Z].
URDATA7/MRXD7 M2
URDATA6/MRXD6 H2
UTOPIA 8-bit Receive Data Bus (I/O/Z) [default] or EMAC receive data bus
URDATA5/MRXD5 L2
[MII] [default] (I/O/Z) or [GMII] (I/O/Z) or [RMII] (I/O/Z)
Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the
URDATA4/MRXD4 L1
URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.
URDATA3/MRXD3 J3
I/O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
URDATA2/MRXD2 J1
pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
URDATA1/MRXD1/
pins) to select the MII, RMII, GMII, or RGMII EMAC interface. (For more details,
H3
RMRXD1
see Section 3, Device Configuration).
URDATA0/MRXD0/
J2
RMRXD0
(1) These pins function as open-drain outputs when configured as PCI pins.
Copyright © 2005–2012, Texas Instruments Incorporated Device Overview 37
Submit Documentation Feedback
Product Folder Link(s): TMS320C6455

Table of Contents

Other manuals for Texas Instruments TMS320C6455

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Texas Instruments TMS320C6455 and is the answer not in the manual?

Texas Instruments TMS320C6455 Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320C6455
CategorySignal Processors
LanguageEnglish

Related product manuals