Texas Instruments TMS320C6455 User Manual

TMS320C6455
www.ti.com SPRS276M –MAY 2005–REVISED MARCH 2012
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE
(1)
IPD/IPU
(2)
DESCRIPTION
NAME NO.
URDATA7/MRXD7 M2
URDATA6/MRXD6 H2
UTOPIA 8-bit Receive Data Bus (I) [default] or EMAC receive data bus for MII
URDATA5/MRXD5 L2
[default], RMII, or GMII
URDATA4/MRXD4 L1
Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the
URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.
URDATA3/MRXD3 J3
I
URDATA2/MRXD2 J1
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC receive data pins for MII [default], RMII, or GMII
URDATA1/MRXD1/
H3
(MRXD[x:0]) (I). MACSEL[1:0] dependent.
RMRXD1
URDATA0/MRXD0/
J2
RMRXD0
Transmit cell available status output signal from UTOPIA slave (O).
• 0 indicates a complete cell is NOT available for transmit
• 1 indicates a complete cell is available for transmit
UXCLAV/GMTCLK K5 O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC GMII transmit clock (GMTCLK) (O). MACSEL[1:0] dependent.
UTOPIA transmit source clock (UXCLK) driven by Master ATM Controller (I) or
when the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
UXCLK/MTCLK/ pin is either EMAC MII [default] or GMII transmit clock (MTCLK) (I) or the
N4 I
RMREFCLK EMAC RMII reference clock (RMREFCLK) (I). The EMAC function is controlled
by the MACSEL[1:0] (AEA[10:9] pins). For more detailed information, see
Section 3, Device Configuration.
UTOPIA transmit Start-of-Cell signal (O). This signal is output by the UTOPIA
Slave on the rising edge of the UXCLK, indicating that the first valid byte of the
cell is available on the 8-bit Transmit Data Bus (UXDATA[7:0]).
UXSOC/MCOL K3 I/O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is the EMAC collision sense (MCDL) (I) for MII [default] or GMII.
MACSEL[1:0] dependent.
UTOPIA transmit interface enable input signal [default] (I) or when the UTOPIA
UXENB/ MTXEN/ peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either the
J5 I/O/Z
RMTXEN EMAC transmit enable (MTXEN) (O) for MII [default], RMII, or GMII.
MACSEL[1:0] dependent.
UXDATA7/MTXD7 N5
UXDATA6/MTXD6 M3
UTOPIA 8-bit transmit data bus (O) [default] or
UXDATA5/MTXD5 L5
EMAC transmit data bus for MII [default], RMII, or GMII.
UXDATA4/MTXD4 L3
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the
UXDATA3/MTXD3 K4
O/Z UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.
UXDATA2/MTXD2 M4
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
UXDATA1/MTXD1/ pins function as EMAC transmit data pins (MTXD[x:0]) (O) for MII, RMII, or
L4
RMTXD1 GMII. MACSEL[1:0] dependent.
UXDATA0/MTXD0/
M1
RMTXD0
Copyright © 2005–2012, Texas Instruments Incorporated Device Overview 39
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Texas Instruments TMS320C6455 Specifications

General

Clock Speed	1.0 GHz
Core Count	1
On-Chip RAM	Yes
Data Width	32-bit
Data Bus Width	64-bit
Operating Voltage	1.2 V
I/O Voltage	3.3 V
Instruction Set	TMS320C64x+
Memory	DDR2
Package Type	BGA
External Memory Interface	EMIF
Interfaces	I2C, SPI

Summary

1 Features

2 Device Overview

2.1 Device Characteristics

2.2 CPU (DSP Core) Description

Details the C64x+ CPU core, functional units, register files, and data paths.

2.3 Memory Map Summary

2.4 Boot Sequence

Explains the process of initializing the DSP's memory and registers at reset.

3 Device Configuration

3.1 Device Configuration at Device Reset

Details configuration pins (AEA, ABA, PCI_EN) for boot mode, clock source, and endianness.

3.2 Peripheral Configuration at Device Reset

3.4 Device State Control Registers

3.5 Device Status Register Description

5 C64x+ Megamodule

5.1 Memory Architecture

Describes the L2, L1P, and L1D memory configurations and sizes.

5.2 Memory Protection

5.3 Bandwidth Management

6 Device Operating Conditions

6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

Specifies stress ratings for voltage, temperature, and other conditions beyond which damage may occur.

6.2 Recommended Operating Conditions

Lists recommended operating ranges for supply voltages, input/output, and temperatures.

6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Details electrical characteristics under specified operating conditions.

7 C64x+ Peripheral Information and Electrical Specifications

7.1 Parameter Information

7.3 Power Supplies

Covers power supply sequencing, decoupling, and power-down operation.

7.4 Enhanced Direct Memory Access (EDMA3) Controller

Details EDMA3 features like transfer dimensions, PaRAM entries, and DMA channels.

7.5 Interrupts

7.6 Reset Controller

Describes different reset types (POR, Warm, Max, System, CPU) and their effects.

7.7 PLL1 and PLL1 Controller

Details PLL1 controller operation, clocks, and registers for frequency synthesis.

7.8 PLL2 and PLL2 Controller

Describes PLL2 controller operation, clocks, and registers for EMAC and DDR2 memory.

7.9 DDR2 Memory Controller

Explains DDR2 interface, device-specific information, and memory topologies.

7.10 External Memory Interface A (EMIFA)

Covers EMIFA interface capabilities for various external devices and timing.

7.11 I2C Peripheral

Describes the I2C module, its features, and device-specific information.

7.12 Host-Port Interface (HPI) Peripheral

7.13 Multichannel Buffered Serial Port (McBSP)

7.14 Ethernet MAC (EMAC)

Describes EMAC module, interface modes (MII, RMII, GMII, RGMII), and control modules.

7.15 Timers

7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)

7.17 Enhanced Turbo Decoder Coprocessor (TCP2)

7.18 Peripheral Component Interconnect (PCI)

7.20 Serial RapidIO (SRIO) Port

7.22 Emulation Features and Capability