TMS320C6455
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SPRS276M –MAY 2005–REVISED MARCH 2012
31 8
Reserved
R-0x00
7 2 1 0
Reserved DDR2CTL EMIFACTL
R-0x00 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-5. Peripheral Configuration Register 1 (PERCFG1) - 0x02AC 002C
Table 3-8. Peripheral Configuration Register 1 (PERCFG1) Field Descriptions
Bit Field Value Description
31:2 Reserved Reserved.
1 DDR2CTL Mode Control for DDR2 Memory Controller. Once this bit is set to 1, it cannot be changed to 0.
0 Set DDR2 to disabled
1 Set DDR2 to enabled
0 EMIFACTL Mode control for EMIFA. Once this bit is set to 1, it cannot be changed to 0. This bit defaults to 1 if
EMIFA 8-bit ROM boot is used (BOOTMODE[3:0] = 0100b).
0 Set EMIFA to disabled
1 Set EMIFA to enabled
Copyright © 2005–2012, Texas Instruments Incorporated Device Configuration 65
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