ARM Cortex-M4 - Page 231

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-15
ID121610 Non-Confidential
When you write to the ICSR, the effect is Unpredictable if you:
• write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
• write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
[25] PENDSTCLR WO SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is
Unknown .
[24] - - Reserved.
[23] Reserved for
Debug use
RO This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
[21:18] - - Reserved.
[17:12] VECTPENDING RO Indicates the exception number of the highest priority pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK
registers, but not any effect of the PRIMASK register.
[11] RETTOBASE RO Indicates whether there are preempted active exceptions:
0 = there are preempted active exceptions to execute
1 = there are no active exceptions, or the currently-executing exception is the only active
exception.
[10:9] - - Reserved.
[8:0]
VECTACTIVE
a
RO Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
a
of the currently active exception.
Note
Subtract 16 from this value to obtain the CMSIS IRQ number required to index into the
Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers, see
Table 2-5 on page 2-6.
a. This is the same value as IPSR bits[8:0], see Interrupt Program Status Register on page 2-6.
Table 4-15 ICSR bit assignments (continued)
Bits Name Type Function