The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-7
ID121610 Non-Confidential
UQASX {Rd,} Rn, Rm
Unsigned Saturating Add and Subtract with Exchange - page 3-103
UQSAX {Rd,} Rn, Rm
Unsigned Saturating Subtract and Add with Exchange - page 3-103
UQSUB16 {Rd,} Rn, Rm
Unsigned Saturating Subtract 16 - page 3-105
UQSUB8 {Rd,} Rn, Rm
Unsigned Saturating Subtract 8 - page 3-105
USAD8 {Rd,} Rn, Rm
Unsigned Sum of Absolute Differences - page 3-71
USADA8 {Rd,} Rn, Rm, Ra
Unsigned Sum of Absolute Differences and Accumulate - page 3-72
USAT Rd, #n, Rm {,shift #s}
Unsigned Saturate Q page 3-96
USAT16
Rd, #n, Rm Unsigned Saturate 16 Q page 3-97
UASX {Rd,} Rn, Rm
Unsigned Add and Subtract with Exchange GE page 3-64
USUB16 {Rd,} Rn, Rm
Unsigned Subtract 16 GE page 3-73
USUB8 {Rd,} Rn, Rm
Unsigned Subtract 8 GE page 3-73
UXTAB {Rd,} Rn, Rm,{,ROR #}
Rotate, extend 8 bits to 32 and Add - page 3-112
UXTAB16 {Rd,} Rn, Rm,{,ROR #}
Rotate, dual extend 8 bits to 16 and Add - page 3-112
UXTAH {Rd,} Rn, Rm,{,ROR #}
Rotate, unsigned extend and Add Halfword - page 3-112
UXTB {Rd,} Rm {,ROR #n}
Zero extend a Byte - page 3-117
UXTB16 {Rd,} Rm {,ROR #n}
Unsigned Extend Byte 16 - page 3-117
UXTH {Rd,} Rm {,ROR #n}
Zero extend a Halfword - page 3-117
VABS.F32 Sd, Sm
Floating-point Absolute - page 3-128
VADD.F32 {Sd,} Sn, Sm
Floating-point Add - page 3-129
VCMP.F32 Sd, <Sm | #0.0>
Compare two floating-point registers, or one
floating-point register and zero
FPSCR page 3-130
VCMPE.F32 Sd, <Sm | #0.0>
Compare two floating-point registers, or one
floating-point register and zero with Invalid Operation
check
FPSCR page 3-130
VCVT.S32.F32 Sd, Sm
Convert between floating-point and integer - page 3-131
VCVT.S16.F32 Sd, Sd, #fbits
Convert between floating-point and fixed point - page 3-132
VCVTR.S32.F32 Sd, Sm
Convert between floating-point and integer with
rounding
- page 3-131
VCVT<B|H>.F32.F16 Sd, Sm
Converts half-precision value to single-precision - page 3-133
VCVTT<B|T>.F32.F16 Sd, Sm
Converts single-precision register to half-precision - page 3-133
VDIV.F32 {Sd,} Sn, Sm
Floating-point Divide - page 3-134
VFMA.F32 {Sd,} Sn, Sm
Floating-point Fused Multiply Accumulate - page 3-135
VFNMA.F32 {Sd,} Sn, Sm
Floating-point Fused Negate Multiply Accumulate - page 3-136
VFMS.F32 {Sd,} Sn, Sm
Floating-point Fused Multiply Subtract - page 3-135
Table 3-1 Cortex-M4 instructions (continued)
Mnemonic Operands Brief description Flags Page
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