Digital Modules
3-26
Programmable Logic Controllers S7-300 Module Data
A5E00105505-03
3.9.1 Synchronicity
Characteristics
Reproducible (i.e. same length) reaction times are achieved for the SIMATIC with
an equidistant DP bus cycle and synchronization of the following free running
single cycles:
• Free running of the user program. The length of the cycle time can vary due to
acyclic program branches.
• Free running, variable DP cycle at the PROFIBUS subnetwork
• Free running cycle at the DP slave back plane bus.
• Free running cycle during signal processing and conversion in the electronic
modules of the DP slave.
In the case of equidistance the DP cycle runs in phase and with the same length.
The procedure levels of a CPU (OB 61 to OB 64) and the synchronous peripheral
are synchronized in this cycle. The E/A data are therefore transferred at defined
and consistent time intervals (clock synchronicity).
Requirements
• The DP-Master and DP-Slave must support the synchronicity. They require
STEP 7 from Version 5.2.
Module filtering mode Synchronicity
In synchronous operation, the following conditions apply:
Filter and processing time T
WE
between reading the current value
and loading it into the transfer buffer
(the specified value for T
WE
applies, independent of the activation of
the hardware interrupt or diagnosis)
255 to 345 s
including an input delay time of 100 s
T
DPmin
2.5 ms
Diagnostic interrupt max. 4 x T
DP
Note
In “synchronous” mode the input delay of the inputs is always set to 100 s
independent of the input delay parameterized in STEP 7
Further information
Further information on clock synchronicity is given in the Online help of STEP 7, in
the manual Local peripheral system ET 200Mand in the manual
Clock synchronicity.
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