Analog Modules
4-100
Programmable Logic Controllers S7-300 Module Data
A5E00105505-03
Basic error (operational limit at 25 C, referred to input
range)
• Voltage input " 1 V " 0.2 %
" 5 V " 0.25 %
" 10 V " 0.2 %
1 to 5 V; " 0.25 %
• Current input " 20 mA " 0.2 %
0 to 20 mA; " 0.2 %
4 to 20 mA: " 0.2 %
Temperature error (with
reference to the input range)
" 0.004 %/K
Linearity error (with
reference to the input range)
" 0.03%
Repeat accuracy (in the
steady state at 25 C,
referred to the input range)
" 0.1 %
Status, interrupts, diagnostics
Interrupts
• Hardware interrupt
• Diagnostic interrupt
Parameters can be
assigned
Parameters can be
assigned
Diagnostic functions
• Group error display
• Diagnostics information
read-out
Red LED (SF)
Possible
Data for Selecting a Sensor
Input range (rated
values)/Input resistance
• Voltage "1 V
" 5 V
" 10 V
1 to 5 V;
/10 MΩ
/100 kΩ
/100 kΩ
/100 kΩ
• Current " 20 mA
0 to 20 mA;
4 to 20 mA:
/50 Ω
/50 Ω
/50 Ω
Maximum input voltage for
voltage input (destruction
limit)
max. 20 V continuous;
75 V for max. 1 s
(duty factor 1:20)
Maximum input current for
current input (destruction
limit)
40 mA
Connection of the sensor
• For measuring voltage Possible
• For measuring current
As two-wire transmitter
As four-wire transmitter
Possible
Possible
• Load of the 2–wire
measurement
transducer
(at L+ = DC 24 V)
max. 820 Ω
Characteristic linearization None
4.20.1 Synchronicity
Characteristics
Reproducible (i.e. same length) reaction times are achieved with the SIMATIC with
an equidistant DP bus cycle and the synchronization of the following free running
single cycles:
• Free running of the user program. The length of the cycle time can vary due to
acyclic program branching.
• Free running, variable DP cycle at the PROFIBUS subnetwork
• Free running cycle at the DP slave backplane bus.
• Free running cycle during the signal processing and conversion in the electronic
modules of the DP slave.
In the case of equidistance the DP cycle runs in phase and with the same length.
In this cycle the processing levels of a CPU (OB 61 to OB 64) and the
synchronous peripheral are synchronized. The I/O data are therefore transferred at
defined and consistent time intervals (clock synchronicity).