ST STM32F101 series Reference Manual

Revision history RM0008
1115/1128 DocID13902 Rev 15
17-May-
2011
13
Updated SPI table in Section 9.1.11: GPIO configurations for device peripherals on
page 166
Updated bit descriptions in Section 7.3.1: Clock control register (RCC_CR) on page 99
and Section 8.3.1: Clock control register (RCC_CR) on page 132
TIMERS:
TIM1&TIM8: Updated example and definition of DBL bits in Section 14.4.19: TIM1&TIM8
DMA control register (TIMx_DCR). Added example related to DMA burst feature and
description of DMAB bits in Section 14.4.20: TIM1&TIM8 DMA address for full transfer
(TIMx_DMAR).
TIM2 to TIM5: added example and updated definition of DBL bits in Section 15.4.17:
TIMx DMA control register (TIMx_DCR). Added example related to DMA burst feature
and description of DMAB bits in Section 15.4.18: TIMx DMA address for full transfer
(TIMx_DMAR). Updated definition of DBL bits in Section 15.4.17: TIMx DMA control
register (TIMx_DCR).
WWDG
Updated Section 20.2: WWDG main features.
Updated Section 20.3: WWDG functional description to remove paragraph related to
counter reload using EWI interrupt.
I2C:
Updated BERR bit description in Section 26.6.6: I2C Status register 1 (I2C_SR1).
Updated Note Note: in Section 26.6.8: I2C Clock control register (I2C_CCR).
Added note 3 below Figure 270: Transfer sequence diagram for slave transmitter on
page 748. Added note below Figure 271: Transfer sequence diagram for slave receiver
on page 749. Modified Section : Closing slave communication on page 749. Modified
STOPF, ADDR, bit description in Section 26.6.6: I2C Status register 1 (I2C_SR1) on
page 770. Modified Section 26.6.7: I2C Status register 2 (I2C_SR2) on page 774.
USART:
Updated Figure 285: Mute mode using address mark detection for Address =1.
ETHERNET:
Removed TX_ETR signal from Figure 330: Media independent interface signals.
SPI:
Modified Slave select (NSS) pin management on page 694 and note on NSS in
Section 25.3.3: Configuring the SPI in master mode
USB OTG FS:
Added caution note related to minimum in Section 28.3.2: Full-speed OTG PHY.
FSMC:
Updated description of DATLAT , DATAST , and ADDSET bits in Section : SRAM/NOR-
Flash chip-select timing registers 1..4 (FSMC_BTR1..4).
Updated description of DATAST and ADDSET bits in Section : SRAM/NOR-Flash write
timing registers 1..4 (FSMC_BWTR1..4).
Table 235. Document revision history (continued)
Date Revision Changes

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English