DocID018909 Rev 11 1097/1731
RM0090 Controller area network (bxCAN)
1112
CAN bit timing register (CAN_BTR)
Address offset: 0x1C
Reset value: 0x0123 0000
This register can only be accessed by the software when the CAN hardware is in
initialization mode.
Bit 2 BOFF: Bus-off flag
This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on
TEC overflow, greater than 255, refer to Section 32.7.6 on page 1084.
Bit 1 EPVF: Error passive flag
This bit is set by hardware when the Error Passive limit has been reached (Receive Error
Counter or Transmit Error Counter>127).
Bit 0 EWGF
: Error warning flag
This bit is set by hardware when the warning limit has been reached
(Receive Error Counter or Transmit Error Counter≥96).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM LBKM
Reserved
SJW[1:0] Res. TS2[2:0] TS1[3:0]
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Reserved
BRP[9:0]
rw rw rw rw rw rw rw rw rw rw
Bit 31 SILM: Silent mode (debug)
0: Normal operation
1: Silent Mode
Bit 30 LBKM
: Loop back mode (debug)
0: Loop Back Mode disabled
1: Loop Back Mode enabled
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:24 SJW[1:0]
: Resynchronization jump width
These bits define the maximum number of time quanta the CAN hardware is allowed to
lengthen or shorten a bit to perform the resynchronization.
t
RJW
= t
q
x (SJW[1:0] + 1)
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 TS2[2:0]
: Time segment 2
These bits define the number of time quanta in Time Segment 2.
t
BS2
= t
q
x (TS2[2:0] + 1)
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