STMicroelectronics STM32F405 User Manual

Revision history RM0090
1708/1731 DocID018909 Rev 11
19-Oct-2012
2
(continued)
SDIO:
Updated value and description for bits [45:40] and [7:1] in Table 175:
R4 response. Updated value at bits [45:40] in Table 177: R5
response.
CAN:
Updated Figure 335: Dual CAN block diagram.
Modified definition of CAN2SB bits in Section : CAN filter master
register (CAN_FMR).
Added register access in Section 32.9: CAN registers
ETHERNET:
Updated standard for precision networked clock synchronization in
Section 33.1: Ethernet introduction and Section 33.2.1: MAC core
features.
Updated CR bit definition in Section : Ethernet MAC MII address
register (ETH_MACMIIAR).
Replace RTPR by PM bit in Table 191: Source address filtering.
USB OTG FS
Updated remote wakeup signaling bit and the resume
interrupt in Section : Suspended state.
Added peripheral register access in Section 34.16: OTG_FS control
and status registerss.
Updated INEPTXSA description in OTG_FS_DIEPTXFx.
Changed PHYSEL from bit 7 to bit 6 of the OTG_FS_GUSBCFG
register.
USB OTG HS
Updated remote wakeup signaling bit and the resume
interrupt in Section : Suspended state.
Added peripheral register access in Section 35.12: OTG_HS control
and status registers.
Updated OTG_HS_CID reset value.
Updated INEPTXSA description in OTG_HS_DIEPTXFx.
Updated FSLSPCS for LS host mode, added PHYSEL in Section :
OTG_HS host configuration register (OTG_HS_HCFG).
Renamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of
the OTG_HS_GUSBCFG register.
Updated OTG_HS_DIEPEACHMSK1 and
OTG_HS_DOEPEACHMSK1 reset values.
Table 310. Document revision history (continued)
Date Version Changes

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English