DocID018909 Rev 11 1709/1731
RM0090 Revision history
1726
19-Oct-2012
2
(continued)
FSMC:
Updated step b) in Section 36.3.1: Supported memories and
transactions.
Updated Table 196: FSMC_BTRx bit fields.
Changed Clock divide ration min in Table 241: Programmable
NAND/PC Card access parameters.
Updated case of synchronous accesses in Section 36.5: NOR
Flash/PSRAM controller.
Changed minimum value for ADDSET to 0 in Table 203, Table 206,
Table 207, Table 209, and Table 210.
Move note from Figure 435: Mode1 write accesses and Figure 434:
Mode1 read accesses. Move note from Figure 437: ModeA write
accesses to Figure 436: ModeA read accesses.
Updated Section : WAIT management in asynchronous accesses.
Added register access in Section 36.5.6: NOR/PSRAM control
registers and Section 36.6.2: NAND Flash / PC Card supported
memories and transactions.
Removed caution note in Section 36.6.1: External memory interface
signalss.
Updated Table 244: 16-bit PC Card.
Updated step 3 in Section 36.6.4: NAND Flash operations.
Updated Figure 453: Access to non ‘CE don’t care’ NAND-Flash and
note below in Section 36.6.5: NAND Flash pre-wait functionality.
Updated access to I/O Space in Section 36.6.7: PC
Card/CompactFlash operationss. Updated Table 246: 16-bit PC-Card
signals and access type. Updated BUSTURN bit definition in
Section : SRAM/NOR-Flash chip-select timing registers 1..4
(FSMC_BTR1..4)). Changed bits 16 to 19 to BUSTURN in Section :
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)
DEBUG:
Updated Section 38.4.3: Internal pull-up and pull-down on JTAG
pins.
Electronic signature
Updated Section 39: Device electronic signature introduction.
Updated REV_ID[15:0] to add revision Z in Section 39.1: Unique
device ID register (96 bits).
Updated address and example in Section 39.2: Flash size.
Table 310. Document revision history (continued)
Date Version Changes
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