Freescale Semiconductor MC68881 - (Continued}

TABLE OF CONTENTS (Continued}
Paragraph Page
Number Title Number
8.5.1.5
8.5.1.6
8.5.2
8.5.2.1
8.5.2.2
8.5.2.3
8.5.2.4
8.5.2.5
8.5.2.6
8.5.2.7
8.5.2.8
8.5.2.9
8.5.2.10
8.6
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
10.1
10.1.1
10.1.2
10.1.3
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
Conditional Instructions ................................................... 8-18
FSAVE and FRESTORE Instructions .................................... 8-18
MC68881 Detail Timing Tables ............................................... 8-19
Instruction Start-Up ........................................................ 8-25
Transfer Operand .............. . ............................................ 8-26
Input Operand Conversion ............................................... 8-27
Arithmetic Calculation ..................................................... 8-27
Output Operand Conversion ............................................. 8-33
Rounding and Exception Handling ..................................... 8-33
Conditional Termination .................................................. 8-36
Multiple Register Transfer ................................................ 8-37
State Frame Transfer ...................................................... 8-38
Exception Processing ...................................................... 8-39
Main Processor Instruction Overlap Timing .................................... 8-40
Section 9
Functional Signal Descriptions
Address Bus (A0-A4) ................................................................. 9-1
Data Bus (D0-D31) .................................................................... 9-2
Size (SIZE) ............................................................................... 9-2
Address Strobe (AS} .................................................................. 9-3
Chip Select (CS) ........................................................................ 9-3
Read/Write (R/W) ...................................................................... 9-3
Data Strobe (DS) 9-3
Data Transfer and Size Acknowledge (DSACK0, DSACK1) .................. 9-3
Reset (RESET) .......................................................................... 9-4
Clock (CLK) .............................................................................. 9-4
Sense Device (SENSE) ............................................................... 9-5
Power (Vcc and GND) ............................................................... 9-5
No Connect (NC) ....................................................................... 9-6
Signal Summary ....................................................................... 9-6
Section 10
Bus Operation
Basic Transfer Mechanism Overview ............................................. 10-1
32-Bit Port Size ................................................................... 10-2
16-Bit Port Size ................................................................... 10-3
8-Bit Port Size ..................................................................... 10-4
Reset
Operation ........................................................................ 10-5
Chip Select Timing .................................................................... 10-6
Bus Cycle Functional Descriptions ................................................ 10-7
Synchronous Read Cycles ..................................................... 10-9
Asynchronous Read Cycles .................................................... 10-12
Asynchronous Write Cycles ................................................... 10-13
Inter-Cycle Timing Restrictions ..................................................... 10-14
Coprocessor Interface Protocol Restrictions .................................... 10-15
FREESCALE
X
MC68881/MC68882 USER'S MANUAL