10
discussed in 10.5 INTER-CYCLE TIMING RESTRICTIONS). For example, if the MC68881
clock frequency is 12.5 MHz and the MPU clock frequency is 16.67 MHz, this bus cycle
requires three MPU clock cycles since the assertion of DSACKx is recognized by the MPU
on the falling edge of $2. This assumes that the chip-select logic causes the assertion of
CS to
precede
the assertion of AS and DS so that the AS/DS
assertion
to DSACKx assertion
delay is not lengthened by the chip-select logic propagation time.
10.5 INTER-CYCLE TIMING RESTRICTIONS
The bus interface of the MC68881 is designed to operate satisfactorily at any reasonable
clock frequency relationship between the MC68881 and the main processor. In most cases,
differences in the clock frequency of the two devices does not affect the operation of the
bus; and particularly, it does not affect the timing of individual bus cycles. However, there
are some cases where the timing of a bus cycle is modified if the MC68881 is overrun by
the main processor.
During coprocessor interface dialogs, certain bus cycles trigger actions by the FPCP on the
negated edge of data strobe. Operations internal to the FPCP that are initiated in this manner
are
completed within four clock cycles after the negation of DS, but the main processor
may initiate a subsequent asynchronous bus cycle before those internal operations are
completed. In these cases, the MC68881 delays the subsequent asynchronous access by
not responding to the bus cycle (and thus not asserting DSACKx) until the internal oper-
ations are completed. Synchronous accesses (i.e., accesses to the response or save CIR)
execute in the normal manner regardless of preceding accesses. The following is a list of
the bus cycles that initiate internal operations on the negated edge of DS, where a sub-
sequent asynchronous bus cycle might overrun the FPCP and necessitate a delay in the
assertion of DSACKx:
1. A write cycle to the least significant byte of the control CIR
2. A write cycle to the least significant byte of the restore CIR
3. The last write cycle to the least significant byte of the operand CIR during a restore
operation with a busy state frame
4. The first read from the least significant byte of the operand CIR during a save operation
with an idle or busy state frame
In all of these cases, the term least significant byte indicates a transfer of any size that
includes the least significant byte of the referenced CIR and does not indicate that only
byte transfers cause conditions that require delays in subsequent bus cycles.
In addition to the cases just described, the possibility exists that the main processor may
overrun the FPCP if the main processor clock frequency is greater than that of the FPCP.
There are two cases where this might occur:
1. The main processor reads the operand or register select CIR before the FPCP has data
ready for transfer to the main processor.
2. The main processor writes to the operand CIR before the data from the previous write
cycle has been stored internally.
In both of these cases, the FPCP does not respond to the initiation of an asynchronous bus
cycle until the internal data transfers are completed (synchronous bus cycles are not de-
layed).
FREESCALE
10-14
MC68881/MC68882 USER'S MANUAL
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