-- m __
AS is asserted (since CS is system dependent but AS is MPU dependent). This design is
called "early chip select". On the other hand, when CS is asserted after AS has been
asserted, the design is called "late chip select". A late chip-select design may add wait
states to the FPCP accesses.
A timing restriction on CS occurs on a FPCP access followed immediately by a non-FPCP
access. CS, which is asserted during the FPCP access, must negate in time for it to occur
before the assertion of AS of the subsequent non-FPCP access.
To satisfy this timing restriction with an early chip select, neither AS or DS can be used
to generate CS. Figure 10-4 shows some circuits that correctly generate an early chip-select
signal for MPU-based systems. Note that in these circuits only the following terms are
included in the CS equation:
• FC2-FC0=7 -- CPU Space
• A19-A 16 = 2 -- Coprocessor Communications
• A15-A13 = 1 -- Cp-ID One (Freescale Assembler Default)
For systems that use the MC68020 or the MC68030 with an FPCP, the maximum time for
an early chip select is:
tAVCS = tAVSA
where:
tAVCS = Address/function code valid to CS asserted (maximum).
tAVSA = MC68020/MC68030 address/function code valid to AS asserted (AC electrical
specification #11 minimum).
For a 20-MHz MPU and a 25-MHz FPCP:
tAVCS = 10 ns maximum.
The 74AS02 and 74AS30 implementation shown in Figure 10-4 or a PAL implementation
witha maximum decode delay time of 10 ns may be used.
For a 25-MHz and 33-MHz MPU/FPCP system, refer to EB116 entitled
Chip-Select Generation
for a 33.33-MHz MC68030 Microprocessor and a 33.33-MHz MC68882 Floating-Point Co-
processor.
A late chip-select design can use slower (and, therefore, less expensive) logic. To implement
this design, the C-S generation logic should include A-S. Another consideration in using
slower logic is that if a non-FPCP access follows an FPCP access, the CS for the FPCP must
not remain asserted inadvertently during the non-FPCP access. However, AS should be
included in the decode logic as shown in Figure 10-5(A), along with the timing that the
logic provides. When AS is used in an AND gate with the decode logic output as shown
Figure 10-5(B), CS is asserted after the start of the non-FPCP access, as the timing diagram
shows. This implementation in Figure 10-5(B) is incorrect.
10.4 BUS CYCLE FUNCTIONAL DESCRIPTIONS
The FPCP executes three types of bus cycles, according to the direction of the transfer and
the CIR that is selected by the main processor. The three bus cycle types are: synchronous
read cycles, asynchronous read cycles, and asynchronous write cycles. In this context, the
terms synchronous and asynchronous convey slightly different meanings than when they
MC68881/MC68882 USER'S MANUAL
FREESCALE
10-7
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