4.7.1.1 REGISTER-TO-REGISTER INSTRUCTIONS. This class of instructions includes
floating-point data register to floating-point data register moves and the monadic, dyadic
arithmetic, and transcendental instructions. For dyadic arithmetic instructions, the desti-
nation operand is replaced by the result.
FPm <op> FPn ~ FPn
For monadic arithmetic instructions, the operand is the source FPm and the result is placed
into the destination FPn. The source FPm and destination FPn can be the same floating-
point data register.
FPm <op> t FPn
The encoding format for this class of instructions is:
15 14 13 12 11 10 9 8 7 6
, , , , I OPROOESSOR'O I0 I0 0
SOURCE E T,.AT,O
0 0 0 REO,S ER .E ,S.ER
5 4 3 2 t 0
I01010101010
EXTENSION
Table4-12 shows the encoding of the source and destination register field.
Table 4-12. Register Field
Encoding
O0O--FPO 100--FP4
O01--FP1 101--FP5
010--FP2 110--FP6
011--FP3 111--FP7
The extension field indicates the operation to be performed. Table 4-13 lists the extension
field encodings and functions. Also shown are the services requested of the MPU by the
FPCP.
4.7.1.2 EXTERNAL OPERAND-TO-REGISTER INSTRUCTIONS. This class of instructions
includes external operand to floating-point data register move and arithmetic instructions.
External operands are located either in memory or an MPU data register (for B, W, L, or
S data types). Data format conversion from one of the seven memory data formats to the
extended data format is implicit in these instructions. For dyadic arithmetic instructions,
the value in FPn is replaced by the result.
External Operand <op> FPn ~ FPn
For monadic arithmetic instructions, the external operand is the source, and the result is
placed in the destination FPn.
External Operand <op> ~ FPn
The encoding format for this class of instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
J COPROCESSOR EFFECTIVE ADDRESS
1 1 I 1 ID 0 0 0 MODE REGISTER
SOURCE DESTINATION
0 ! 0 FORMAT REGISTER EXTENSION
MC68881/MC68882 USER'S MANUAL
FREESCALE
4-127
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