encoding returned always indicates that the port is 8 bits wide. In order to eliminate the
need for on-chip multiplexing, the FPCP drives data on or receives
data
from only 8 bits
of the data bus, depending on the encoding of A0, A1 and A4 (thus allowing D31, D23,
D15 and D7 of the FPCP to be tied together; D30 to be tied to D22, D14 and D6; D29 to
D21, D13 and D5, etc., as described in SECTION 11 INTERFACING METHODS). Figure 10-
2 shows which bytes of the data bus are driven or received for each encoding of the A0,
A1, and A4 lines.
When the FPCP is used in the 8-bit configuration, most transfers require multiple CIR
transfers to move an entire instruction or data item. The one exception to this is for accesses
to the operand CIR to transfer a byte immediate operand. When an item is larger than one
byte, multiple accesses of the appropriate CIR are required to complete the transfer. In this
case, the correct transfer order must be observed, in addition to the bit and byte alignment
previously discussed. In all cases, each part of an item is transferred with the most sig-
nificant bit aligned with bit 31, 23, 15, or 7 of the FPCP, depending on the value of A0, A1,
and A4 as described in the previous paragraph. With the exception of byte and word
immediate operands, the FPCP never requests the transfer of an item that is not a multiple
of four bytes in length. Immediate byte operands are transferred in a single bus cycle and
are left-aligned with the operand CIR (i.e., they are transferred across D31-D24). All other
operands are transferred through the appropriate CIR in 8-bit units until the entire item is
transferred.
When multiple bus cycles are required to transfer an item, the first operand CIR access
transfers the most significant word of the item; each successive access transfers the next
least significant word. For example, when an extended precision number is moved, the
first operand CIR access is used to transfer bits 95-88 of the operand, the second access
transfers bits 87-80, and the third through twelfth accesses transfer bits 79-72, 71-64,
63-56, 55-48, 47-40, 39-32, 31-24, 23-16, 15-8 and 7-0, respectively, to complete the
operand transfer. Note that the manner in which the operand is read from or written to
memory is transparent to the FPCP, which allows the operand to be stored in memory in
the native format of the main processor.
The amount of data transferred with each access to the operand CIR is dependent on the
state of an instruction dialog and is determined by the FPCP, not the main processor. For
example, if the FPCP issues an evaluate effective address and transfer data primitive with
a length of 12 bytes, 12 accesses of the operand CIR are expected (with each access
transferring one byte). Thus, for an 8-bit port, the main processor is not allowed to transfer
the operand with a series of word or long-word transfers, but must use byte transfers to
move the operand.
10.2 RESET OPERATION
Before the FPCP can be used for any operation after power has been applied to the system,
it must be initialized using a hardware reset function. This is done when power is initially
applied to the system by asserting RESET for at least four clock cycles (with reference to
the FPCP CLK signal) after VCC has reached the nominal operating level. After power has
been stable and the FPCP has executed a power-up reset operation, a subsequent reset
operation may be initiated by asserting ~ for at least two cycles of the FPCP CLK
signal. Note that in order to maintain compatibility with all M68000 Family devices, the
power-on reset pulse for a system should be a minimum of 100 ms, while a 10 clock
minimum (with respect to the clock signal of the slowest M68000 Family device in the
system) should be used for reset operations after power iS stable.
MC68881/MC68882 USER'S MANUAL
FREESCALE
10-5
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