Freescale Semiconductor MC68881 - MC68882 Concurrency - - FMUL Followed by FMUL and FMOVE

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Then, the coprocessor completes the FMOVE by converting the operand and transferring
it to the main processor.
In this example, the MPU continues to examine the response CIR of the MC68881 while it
completes each of the two FMUL instructions. Should an interrupt occur during these times,
the main processor services the interrupt but does not initiate any other instruction.
The MC68882 can execute floating-point instructions concurrently by performing conver-
sions between external binary real data formats (S, D, and X) and the internal extended
format in the conversion unit (CU) while the arithmetic processing unit (APU) is calculating
the result of a preceding instruction. Additional concurrency is provided by making the
floating-point data registers accessible to both the CU and APU simultaneously.
Figure 5-3 shows the same three floating-point instructions executing in an MC68882. As
soon as the operand of the first FMUL instruction has been transferred to the coprocessor,
the main processor begins executing the next instruction, another FMUL instruction with
an external source operand. Provided the operand is a binary real operand and no register
conflict occurs, the coprocessor can transfer and convert the operand while it continues
to calculate the product of the first FMUL instruction. As soon as the operand transfer
completes, the main processor begins executing the FMOVE instruction. Since the CU
contains the converted operand for the second FMUL instruction at this time, it is not
available to convert the source operand of the FMOVE instruction. However, when the APU
completes the rounding phase for the first FMUL instruction, it accepts the operand from
the CU and begins calculations for the second FMUL instruction. The CU now converts the
source operand of the FMOVE instruction to the destination format. The bus interface unit
(BIU) transfers the converted operand to the external destination, completing the second
FMUL instruction.
The effect of the concurrency provided by the MC68882 is to execute three instructions
during a time period equal to the execution time of the first instruction plus the computation
time of the second instruction. Execution of the third instruction is completely overlapped
by the second instruction.
In this example, execution of the second FMUL instruction is partially concurrent with
execution of the first FMUL instruction, and execution of the FMOVE instruction is fully
concurrent with execution of the second FMUL instruction. Some MC68882 instructions
do not execute concurrently. Others execute partially concurrently, and some execute with
full concurrency. However, little concurrency is possible when the operand is in integer or
packed decimal format.
MCBSO2D/MCBB03O
MC68882
FMUL
FMUL
FMOVE
IDLE (1Nl~ RRUPTS.
BUS ARBITRATIO N Art D',,V~ D) ~ 'EX'T '~STR'''TT' ~ 'W J
Figure 5-3. MC68882 Concurrency -- FMUL Followed by FMUL and FMOVE
FREESCALE
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MC68881/MC68882 USER'S MANUAL