(This is always the case if the main processor is the MPU.) The FPCP always sets the PC
bit in the first primitive of a general type instruction that might cause an exception (i.e.,
all of the arithmetic and move single floating-point data register instructions when excep-
tions are enabled), or the take pre-instruction exception primitive for a BSUN trap during
a conditional instruction. By updating the FPIAR in this manner, the FPCP can release the
main processor for concurrent execution after all operands are fetched, and exception
handlers can later locate an instruction that causes an exception. It should be noted that
the PC bit is set in only one primitive response during any instruction dialog, and that the
MC68881 does not issue a protocol violation if the main processor ignores the request to
transfer the PC. The MC68882 issues a protocol violation if the main processor fails to
transfer the PC in response to a request.
Bit [13] in the primitive format, denoted by DR, is the direction bit; it controls the direction
of operand transfers between the main processor and the FPCP. If DR is zero, the direction
of the transfer is from the main processor to the FPCP (a main processor write). If DR is
one, the direction of the transfer is from the FPCP to the main processor (a main processor
read). If the operation indicated by a given response primitive does not involve an explicit
operand transfer, the value of this bit is dependent on the particular primitive encoding.
NOTE
All primitives issued by the MC68881, with the exception of the null primitive,
have the CA bit equal to one, causing the MPU to check the response CIR after
any service is performed. This allows the MC68881 to assure correct internal
operation and to report exceptions immediately after a service is performed.
However, the MC68882 may occasionally issue an evaluate <ea> and transfer
data primitive with CA equal to zero. This is done in cases where internal oper-
ations are not adversely affected by the omission of the read of the response CIR
after the operand transfer.
The following paragraphs describe the response primitive encodings used by the FPCP
and the expected main processor response to each one in detail.
7.4.2.1 NULL PRIMITIVE. This primitive is used by the FPCP to synchronize operation
with the main processor and to allow concurrent execution by the main processor. The
format of the null primitive is shown in Figure 7-8. In addition to the variable bits CA and
PC previously discussed, the null primitive uses three other variable bits to identify the
required action to be taken by the main processor. Bit [8], denoted by IA, is used to specify
that the main processor may process pending interrupts if necessary. Bit [1], denoted by
PF, is used to indicate the status of the FPCP during concurrent instruction execution. If
the PF bit is zero, the FPCP is executing an instruction; otherwise it is idle. Bit [0], denoted
by TF, is used to communicate the true or false result of a conditional evaluation. If TF
equals one, the condition is true; otherwise it is false.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I i I I I
I I I
Figure 7-8. Null Primitive Format
MC68881/MC68882 USER'S MANUAL FREESCALE
7-11
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