10
are assumed to transfer a full 16 bits to the word address selected by A1 (except for the
case of an immediate byte operand, as discussed in a following paragraph). The DSACK
encoding returned always indicates that the port is 16 bits wide; individual bytes cannot
be accessed in this configuration.
In order to eliminate the need for on-chip multiplexing, the FPCP drives data on or receives
data from only 16 bits of the data bus, depending on the encoding of A1 and A4 (thus
allowing D31 and D15 of the FPCP to be tied together, D30 to be tied to D14, D29 to D13,
etc., as described in SECTION 11 INTERFACING METHODS. For all accesses with A4 equal
to zero, or with A4 equal to one and A1 equal to zero, data is transferred across D31-D16.
Data is transferred across D15-D0 when A4 and A1 are both equal to one.
When the FPCP is used in the 16-bit configuration, most CIR accesses transfer an entire
instruction or data item in a single bus cycle. The one exception to this is for accesses to
the operand CIR, which is used to transfer large items such as
floating-point numbers and
state frames. When an item is larger than two bytes, multiple accesses of the operand CIR
are required to complete the transfer. In this case, the correct transfer order must be
observed, in addition to the bit and byte alignment previously discussed. In all cases, each
part of an item is transferred with the most significant bit aligned with bit 31 or bit 15 of
the operand CIR, depending on the value of A4 and A1 as described in the
previous
paragraph. With the exception of byte and word immediate operands, the FPCP never
requests the transfer of an item that is not a multiple of four bytes in length. Immediate
byte operands are transferred in a single bus cycle and are left-aligned with the operand
CIR (i.e., they are transferred across D31-D24). All other operands are transferred through
the operand CIR in 16-bit units until the entire item is transferred.
When multiple bus cycles are required to transfer an item, the first operand CIR access
transfers the most significant word of the item; each successive access transfers the next
least significant word. For example, when an extended precision number is moved, the
first operand CIR access is used to transfer bits 95-80 of the operand, the second access
transfers bits 79-64, and the third through sixth accesses transfer bits 63-48, 47-32, 31-16
and 15-0, respectively, to complete the operand transfer. Note that the manner in which
the operand is read from or written to memory is transparent to the FPCP, which allows
the operand to be stored in memory in the native format of the main processor.
The amount of data transferred with each access to the operand CIR is dependent on the
state of an instruction dialog and is determined by the FPCP, not the main processor. For
example, if the FPCP issues an evaluate effective address and transfer data primitive with
a length of 12 bytes, six accesses of the operand CIR are expected (with each access
transferring two bytes). Thus, for a 16-bit port, the main processor is not allowed to transfer
the operand with a series of long-word or byte transfers, but must use word transfers to
move the operand.
10.1.3 8-Bit Port Size
When the SIZE signal is low, the FPCP port size is defined to be eight bits. In most cases,
this configuration is statically selected by connecting the SIZE pin directly to GND, although
dynamic port size selection is possible if the proper timing constraints
are followed for the
SIZE and A0 pins. In this case, the value of A0 is used to select the correct byte address,
rather than to configure the data port size. When the FPCP is configured in this manner,
all CIR accesses transfer one byte to the address selected by A4-A0, and the DSACK
FREESCALE
10-4
MC68881/MC68882 USER'S MANUAL
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