9.4 ADDRESS STROBE (AS)
This active-low input signal indicates that there is a valid address on the address bus, and
both the chip select (CS) and read/write (R/W) signal lines are valid.
9.5 CHIP SELECT (CS)
This active-low input signal enables the main processor access to the FPCP coprocessor
interface registers. When operating the FPCP as a peripheral processor, the chip-select
decode is system dependent (i.e., like the chip select on any peripheral). The CS signal
must be valid (either asserted or negated) when AS is asserted. Refer to 10.3 Chip Select
Timing
for further discussion of timing restrictions for this signal.
9.6 READ/WRITE (R/W)
This input signal indicates the direction of a bus transaction (read/write) by the main
processor. A logic high (1) indicates a read from the FPCP, and a logic low (0) indicates a
write to the FPCP. The RAN signal must be valid when AS is asserted.
9.7 DATA STROBE (DS)
This active-low input signal indicates that there is valid data on the data bus during a write
bus cycle.
9.8 DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACK1, DSACK0)
These active-low, three-state output signals indicate the completion of a bus cycle to the
main processor. The FPCP asserts both the DSACK1 and DSACK0 signals when the MPU
asserts CS.
If the bus cycle is a r~ain processor read, the FPCP asserts DSACK1 and DSACK0 signals
to indicate that the information on the data bus is valid, (Both DSACK signals can be
asserted in advance of the valid data being placed on the bus.) If the bus cycle is a main
processor write to the FPCP, DSACK1 and DSACK0 are used to acknowledge acceptance
of the data by the FPCP.
The FPCP also uses DSACK1 and DSACK0 signals to dynamically indicate to the MPU the
port size (system data bus width) on a cycle-by-cycle basis. Depending upon which of the
two DSACK pins is asserted for a bus cycle, the MPU assumes data has been transferred
to/from an 8-, 16-, or 32-bit wide data port. Table 9-3 lists the DSACK assertions that are
used by the FPCP for the various bus cycles over the various system data bus configurations.
Refer to 10.1
BASIC TRANSFER MECHANISM
OVERVIEW for details of data bus utilization
by the FPCP.
Table 9-3 indicates that all accesses using a 32-bit bus with A4 equal to zero are to 16-bit
registers. The FPCP implements all 16-bit coprocessor interface registers on data lines
D31-D16 (to eliminate the need for on-chip multiplexors); however, the MPU expects 16-
bit registers that are located in a 32-bit port at odd word addresses (A1 ~- 1) to be imple-
mented on data lines D15-D0. For accesses to these registers when configured for 32-bit
MC68881/MC68882 USER'S MANUAL FREESCALE
9-3
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