T
Timing,
Arithmetic Operation, 8-12
MC68881, 8-12
MC68882, 8-12
Asynchronous
Read Cycle, 10-12
Write Cycle, 10-13
Calculation
Example, 8-16
Phase,
8-3
Chart, Instruction Execution, 8-6
Chip Select, 10-6
Coprocessor
Interface Overhead,
8-8, 8-9
Diagrams, Foldout
Effective Address Calculation, 8-12
Late Chip Select, 10-9
Restrictions, Inter-Cycle, 10-14
Round/Store Result Phase, 8-4
Start-Up Phase, 8-3
Synchronous Read Cycle, 10-9
Trace Exception, 6-25
Transcendental Instruction Accuracy, 4-7
Transfer Mutt/pie
Coprocessor
Registers
Example, 7-16
Primitive, 7-15
Format, 7-15
Transfer Single Main Processor Register
Primitive, 7-14
Format, 7-14
Transfers, Interprocessor, 7-8
Types,
CPU Space, 7-2
Data, 3-3, 3-13
Typical
Coprocessor Configuration, 1-6
Execution Timing Assumptions, 8-11
U
Undefined Command Word, 4-133
Underfiow
Exception, 6-11
Processing, 4-15
UNFL Exception, 6-11
Unit, Bus Interface, 1-6
--Vw
Valid Effective Address Codes, 7-14
VCC
Decoupling, 9-6
Pin Asskjnments, 9-6
Vector Numbers, Exception, 7-17
W
Write Cycles, Asynchronous, 10-13
X
X Format, 3-12
Z
Zeros, 3-5
NUMERALS m
16-bit
Bus
Coprocessor Connection, 11-2
Peripheral Connection, 11-3, 11-4
Port Size, 10-3
32-bit
Bus Coprocessor Connection, 11-1
Port Size, 10-2
8-bit
Bus
Coprocessor Connection, 11-2, 11-3
Peripheral Connection, 11-3, 11-4
Port Size, 10-4
FREESCALE
INDEX-10
MC68881/MC68882 USER'S MANUAL
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