of the operation. Second; the FPCP provides 32 conditional tests that are supported in
hardware by the M68000 Family coprocessor interface. This mechanism allows conditional
instructions that test floating-point conditions to be coded in exactly the same way as the
integer conditional instructions. The evaluation of the conditional test by the FPCP is per-
formd automatically. The combination of the consistent setting of the condition code bits
and the simple programming of conditional instructions gives the MC68020/MC68030 and
FPCP combination a very flexible, high-performance method of altering program flow based
on floating-point results.
One important programming consideration is that the inclusion of the NAN data type in
the IEEE floating-point number system requires each conditional test to include the NAN
condition code bit in its Boolean equation. Because a comparison of a NAN with anything
is unodered (i.e., it is impossible to determine if a NAN is bigger or smaller than an in-
range number), the compare instruction sets the NAN condition code bit when an unordered
compare is attempted. All arithmetic instructions also set the NAN bit if the result of an
operation is a NAN. The conditional instructions interpret the NAN condition code bit equal
to one as the unordered condition.
The inclusion of the unordered condition in floating-point branches destroys the familiar
trichotomy relationship (greater than, equal, less than) that exists for integers. For example,
the opposite of floating-point branch greater than (FBGT) is not floating-point branch less
than or equal (FBLE). Rather, the opposite condition is floating-point branch not greater
than (FBNGT). If the result of the previous instruction was unordered, FBNGT is true;
whereas, both FBGT would be false since unordered fails both of these tests (and sets
BSUN). Compiler programmers should be particularly careful of the lack of trichotomy in
the floating-point branches since it is common for compilers to invert the sense of con-
ditions.
In the following paragraphs, the conditional tests are described in three main categories:
1. IEEE nonaware tests,
2. IEEE aware test, and
3. Miscellaneous.
The set of IEEE nonaware tests is best used:
1. When porting a program from a system that does not support the IEEE standard to
a conforming system, or
2. When generating high-level language code that does not support IEEE floating-point
concepts (i.e., the unordered condition).
When using the set of IEEE nonaware tests, the user receives a BSUN exception whenever
a branch is attempted and the NAN condition code bit is set, unless the branch is an FBEQ
or an FBNE. If the BSUN trap is enabled in the FPCR register, the exception causes a trap.
Therefore, the IEEE nonaware program is interrupted if something unexpected occurs.
The IEEE aware branch set should be used in programs that contain ordered and unordered
conditions by compilers and programmers who are knowledgeable of the IEEE standard.
Since the ordered or unordered attribute is explicitly included in the conditional test, the
BSUN bit is not set in the status register EXC byte when the unordered condition occurs.
MC68881/MC68882 USER'S MANUAL
FREESCALE
4-9
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