Freescale Semiconductor MC68881 - Setting Floating-Point Condition Codes; Underflow, Round, Overflow

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4.5.5.1 SETTING FLOATING-POINT CONDITION CODES. Unlike the integer arithmetic
condition codes found in the MC68020/MC68030, which are set uniquely for each instruc-
tion, the floating-point condition codes are either not changed by an instruction or are
always set in the same way by an instruction. Therefore, it is not necessary to include
details of condition code settings for each FPCP instruction in the detailed instruction
descriptions. The following paragraphs describe how condition codes are set for all in-
structions that modify any condition codes.
Refer to 2.3.1 FPSR
Floating-Point Condition Code Byte for a description of the FPSR
condition code byte. The four condition code bits are:
N Sign of Mantissa I Infinity
Z Zero NAN Not-A-Number
These condition code bits differ slightly from integer condition codes. The floating-point
condition codes are not dependent on the type of operation being performed, but rather,
can be set at the end of the operation by examining the result. (The M68000 integer
condition code bits N and Z have this characteristic, but the V and C bits are set differently
for different instructions.) At the end of any floating-point operation, the result is inspected,
and the condition code bits are set or cleared accordingly. For example, if the result of an
operation is a positive normalized number, then all of the condition code bits are set to
zero. If the result is a minus infinity, then the N and I bits are set, and the Z and NAN bits
are cleared;
Refer to 2.3.1 FPSR
Floating-Point Condition Code Byte for a description of the use of these
bits to generate the four conditions required by the IEEE floating-point standard. Refer to
4.4 CONDITIONAL TEST DEFINITIONS for a description of the use of the four condition
code bits to generate the 32 floating-point conditional tests.
415.5.2 UNDERFLOW, ROUND, OVERFLOW. During calculation of an arithmetic result.
the ALU of the FPCP has more precision and range than the 80-bit extended precision
format, However, the final result of these operations is an extended precision floating-
point value. In some cases, an internal result becomes either smaller or larger than can
be represented in extended precision. Also, the operation may have generated a larger
exponent or more bits of precision than can be represented in the chosen rounding pre-
cision. For these reasons, every arithmetic instruction ends by rounding the result and
checking for overflow and underflow.
Atthe completion of an arithmetic operation, the internal result is checked to see if it is
too small to be represented as a normalized number in the selected precision. If so, the
underflow (UNFL) bit is set in the FPSR EXC byte. It is also denormalized unless denor-
realization provides a zero value. Denormalizing a number causes a loss of accuracy, but
a zero is not returned unless absolutely necessary. If a number is grossly underflowed, the
FPCP returns a correctly signed zero or the correctly signed smallest denormalized number,
depending on the rounding mode in effect. For more details on underflow, refer to 6.1.5
Underflow.
If no underflow occurs, the internal result is rounded according to the user-selected round-
ing precision and rounding mode. Refer to Figure 6-3 for a detailed description of rounding.
After rounding, the inexact bit (INEX2) is set appropriately. Lastly, the magnitude of the
result is checked to see if it is too large to be represented in the current rounding precision.
If so, the overflow (OVFL) bit is set and a correctly signed infinity or correctly signed largest
FREESCALE
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MC68881/MC68882 USER'S MANUAL