Table 4-21. Effective Address Field Encoding Summary
Assembler
Address Modes Mode Register Data Memory Control Alterable
Syntax
Data
Register Direct 000 reg. no. X -- -- X Dn
Address Register Direct 001 reg. no. -- -- -- X An
Address Register Indirect 010 reg. no. X X X X (An)
Address Register Indirect with Postincrement 011 reg. no. X X -- X (An) +
Address Register Indirect with Predecrement 100 reg. no. X X -- X -(An)
Address Register Indirect with Displacement 101 reg. no. X X X X (d16,An)
Address Register Indirect with Index 110 reg. no. X X X X (d8,An,Xn)
(8-Bit Displacement)
Address Register Indirect with Index 110 reg. no. X X I X X (bd,An,Xn)
(Base Displacement)
J
Memory Indirect Postindexed 110 reg. no. X X X X ({bd,An},Xn,od)
Memory Indirect Preindexed 110 reg. no. X X X X ([bd,An,XnJ,od)
Absolute
Short 111 000 X X X X (xxx).W
Absolute
Long 111 001 X X X X (xxx).L
Program Counter Indirect with Displacement 111 010 X X X -- (d16,PC)
Program Counter Indirect with Index 111 011 X X X -- (d8,PC,Xn)
(8-Bit Displacement)
Progr-~m Counter Indirect with Index 111 011 X X X -- (bd,PC,Xn)
(Base Displacement}
PC Memory Indirect Postindexed 111 011 X X X -- (Ebd,PCl,Xn,od)
PC Memory Indirect Preindexed 111 011 X X X -- ([bd,PC,Xn},od)
Immediate 111 100 X X -- -- #<data>
4.8.5 Destination Register Field
This field is common to all of the arithmetic instructions and the FMOVE to FPn instruc-
tion. This field specifies the floating-point data register that is to be used as the destina-
tion. The result of an operation is always stored in this register, and one of the source
operands is fetched from this register for dyadic instructions.
4.8.6 Conditional Predicate Field
This field is common to all of the conditional instructions and specifies the FPCP condi-
tional test that is to be evaluated for the main processor. Table 4-22 shows the condi-
tional predicate binary encodings for the 32 conditional tests supported by the FPCP.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-139
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