SECTION 10
BUS OPERATION
This section describes the functional characteristics of the MC68881/MC68882 (FPCP) bus
interface and the mechanisms used to execute data transfers between the FPCP and the
main processor. This discussion includes descriptions of the functional characteristics of
individual bus cycles as well as descriptions of the operand transfer protocols that require
multiple bus cycles.
Although the FPCP is designed primarily for use as a coprocessor to the MC68020/MC68030
(MPU), there are no characteristics of the bus operation that preclude the use of the FPCP
as a peripheral device with any other processor. This is because the M68000 Family co-
processor interface utilizes standard bus cycles to transfer instructions and data between
the main processor and coprocessors in a system, with no special signals required for
these transfers. Because of this general-purpose transfer mechanism, the type of the main
processor and the nature of the system bus interface are transparent to the FPCP.
10.1 BASIC TRANSFER MECHANISM OVERVIEW
In order to execute a floating-point instruction, the FPCP and the main processor com-
municate using a series of bus cycles, instructions, and data according to a predefined
protocol as described in 7.5 INSTRUCTION DIALOGS. Most of these bus cycles transfer an
entire item in a single transfer, although large items such as extended precision floating-
point numbers require multiple bus cycles to transfer the entire operand. Also, if an FPCP
port size of 8 or 16 bits is selected, multiple bus cycles can be required to transfer items
that can be transferred with a single cycle over a 32-bit port.
The communications mechanism utilized by the FPCP and the main processor uses a set
of mail-box registers, called the coprocessor interface registers (CIRs), to move data, in-
structions, and control information between the devices. The characteristics of the CIRs
and the manner in which they are used by the FPCP and a main processor are described
in SECTION 7 COPROCESSOR INTERFACE. The discussions in the following paragraphs
are not specific to any particular CIR or instruction protocol, except where noted.
When a single bus cycle is able to accommodate an entire item, the transfer mechanism
is obviously quite simple and the only requirement that must be met is that the bit alignment
of the FPCP and main processor match. Figure 10-1 shows the bit assignment and signif-
icance of the 32-bit data bus of the FPCP, which must be matched to the main processor
(for the MPU, this matching is accomplished by connecting D31 of the FPCP to D31 of the
MC68020, D30 to D30, etc.).
When multiple bus cycles are required to transfer an item, the additional requirements of
correct transfer order and port alignment must also be met. Figure 10-2 shows the data
alignment of the FPCP for each port size. In this figure, if a section of the data bus is shaded
for a particular encoding of SIZE, A4, A1 and A0, that section of the data bus is active
during the transfer (i.e., valid data is expected during a write cycle, and the bus is driven
MC68881/MC68882 USER'S MANUAL
FREESCALE
10-1
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