DSACK encoding returned indicates a 16-bit port size. All of the CIRs in the upper half of
the CIR address range (A4 = 1, offsets $10-$1F) are either 32-bit registers or 16-bit registers
paired with undefined register locations. Therefore, the DSACK encoding used to terminate
accesses in this range indicates a 32-bit port (during a read of the register select CIR, data
bits 15-0 are undefined, reserved, and are driven high). In both of these cases, A4 deter-
'mines the DSACK encoding that is returned, and A1 selects the appropriate word location.
A0 is always one, to select a 32-bit FPCP port size, and thus individual bytes cannot be
accessed in this configuration. Furthermore, the FPCP always expects a full 16 or 32 bits
of data to be transferred during a bus cycle when SIZE is high; A0 is one, and A4 is zero
or one, (with the exception of immediate byte or word operands, as discussed in the next
paragraph).
When the FPCP is used in a 32-bit configuration, most CIR accesses transfer an entire
instruction or data item in a single bus cycle. The one exception to this is for accesses to
the operand CIR, which is used to transfer large items such as floating-point numbers and
state frames. When an item is larger than four bytes, multiple accesses of the operand CIR
are required to complete the transfer. In this case, the correct transfer order must be
observed, in addition to the bit and byte alignment previously discussed. In all cases, each
part of an item is transferred with the most significant bit aligned with bit 31 of the operand
CIR (i.e., they are transferred across D31-D24, D31-D16, or D31-D0 for bytes, words, or
long words, respectively). With the exception of byte and word immediate operands, the
FPCP never requests the transfer of an item that is not a multiple of four bytes in length.
An immediate byte or wordoperand is transferred in a single bus cycle and is left-aligned
with the operand CIR. All other operands are transferred through the operand CIR in
32-bit units until the entire item is transferred.
When multiple bus cycles are required to transfer an item, the first operand CIR access
transfers the most significant long word of the item; each successive access transfers the
next least significant long word. For example, when an extended precision number is
moved, the first operand CIR access is used to transfer bits 95-64 of the operand, the
second access transfers bits 63'32, and the third access transfers bits 31-0 to complete
the operand transfer. Note that the manner in which the operand is read from or written
to memory is transparent to the FPCP, which allows the operand to be stored in memory
in the native format of the main processor.
The amount of data transferred with each access to the operand CIR is dependent on the
state of an instruction dialog and is determined by the FPCP, not the main processor. For
example, if the FPCP issues an evaluate effective address and transfer data primitive with
a length of 12 bytes, three accesses of the operand CIR are expected (with each access
transferring four bytes). Thus, for a 32-bit port, the main processor is not allowed to transfer
the operand with a series of word or byte transfers, but must use long-word transfers to
move the operand.
10.1.2 16-Bit Port Size
When SIZE is high and A0 is low, the FPCP port size is defined to be 16 bits. In most cases,
this configuration is statically selected by connecting the SIZE and A0 pins directly to VCC
and GND, respectively, although dynamic port size selection is possible if the proper timing
constraints are followed for the SIZE and A0 pins. Although A0 =0 in this case, this value
is not specifically used to select even byte addresses; rather, it is used to configure the
data port to be 16 bits wide. When the FPCP is configured in this manner, all CIR accesses
MC68881/MC68882 USER'S MANUAL FREESCALE
10-3
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