10.6 COPROCESSOR INTERFACE PROTOCOL RESTRICTIONS
As just described, the FPCP delays asynchronous bus cycles, if necessary, until internal
operations are completed. However, even though the response to these bus cycles is
delayed, the FPCP bus interface unit control logic does detect the beginning of each access
regardless of the state of the execution unit. Thus, it is possible that an access to a CIR
may be detected before the bus interface unit has completed previous operations and
updated status flags to reflect the state of an instruction dialog. This can result in spurious
protocol violations if the coprocessor interface protocol is not strictly observed.
The most important protocol that must be observed is that the come-again request included
by the FPCP in every evaluate effective address and transfer data primitive must not be
ignored by the main processor. For example, if the come-again request is ignored and the
main
processor clock
is much faster than the FPCP clock, the following situation might
Occur:
1. The main processor receives the evaluate effective address and transfer data request
primitive, processes it, and begins to transfer the operand.
2. The last operand part is written to the operand CIR.
3. The main processor ignores the come-again request and begins execution of the next
instruction immediately.
4. The next instruction is an FPCP instruction that the main processor initiates by writing
the command word to the command CIR.
5. Since the internal operand transfer is not complete, the BIU flags still indicate that
the next expected access is to the operand CIR; thus the access to the command CIR
is deemed illegal, and a protocol violation occurs.
In this case, if the main processor follows the protocol and services the come-again request
by reading the response CIR immediately after the last operand CIR access, a null (CA= 1,
IA = 1) primitive may be returned by the MC68881. Since the response CIR read-cycle timing
is synchronous with the MC68881 clock signal, this read cycle allows the main processor
to be synchronized to the MC68881 internal operations. Thus, the next read of the response
CIR normally occurs after internal operations are completed. At that time, the response
encoding is changed to null (CA=0) to allow the main processor to proceed, and the
subsequent access to the command CIR is a legal access.
In addition to the previously mentioned restrictions, the MC68882 may return an evaluate
<ea> and transfer data primitive with CA=0, which does not require the main processor
to read the response register before proceeding to the next instruction. After the last write
to the operand CIR, if the next instruction is another MC68882 instruction, the write to the
command CIR can occur immediately without adverse effects. However, if the read of the
response CIR (which normally follows the write of the command CIR) occurs sooner than
three MC68882 clocks after the completion of the previous operand CIR write operation, a
protocol violation occurs. Therefore, if the main processor is an MC68020 or MC68030, its
clock frequency cannot be more than 1.5 times the frequency of the MC68882 clock.
Otherwise, the read response CIR operation might occur too soon and cause a protocol
violation. A main processor other than an MC68020 or MC68030 must also observe this
timing requirement to avoid a protocol violation.
MC68881/MC68882 USER'S MANUAL FREESCALE
10-15
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