5
f. Transfers the converted operand to the memory destination (without involving the
APU) by using the evaluate <ea> and transfer data primitive with CA=0. This
releases the main processor immediately after the operand is read from the op-
erand CIR.
• If the instruction is an FMOVE.X FPm,<ea>, the CU does the following:
a. Prefetches the source operand from FPm, unless the instruction currently operating
in the APU uses FPm as a destination. In that case, the CU waits until the APU is
idle before prefetching.
b. If the data type of the source operand is unnormalized, denormalized, or NAN,
waits until the APU is idle and hands off the instruction to the APU.
c. Transfers the converted operand to the memory destination (without involving the
APU) by using the evaluate <ea> and transfer data primitive with CA=0. This
releases the main processor immediately after the operand is read from the op-
erand CIR.
• If the instruction is listed in Table 5-4 and if the source (FPm) and destination (FPn or
FPc:FPs) are all floating-point data registers, the CU does the following:
a. Releases the main processor.
b. Prefetches the source operand from FPm if possible.
c. Waits until the APU is idle and hands off the instruction to the APU.
• If the instruction is listed in Table 5-4 and if the source is external to the MC68882,
the CU does the following:
a. Prefetches the source operand from memory by using the evaluate <ea> and
transfer data primitive with CA= 0. This releases the main processor immediately
after the source operand is written to the operand CIR.
b. If the source operand format is single or double, precision, converts the source
operand to the extended precision internal format.
c. Creates a tag that represents the data type of the converted source operand (nor-
malized, unnormalized, denormalized, zero, infinity, or NAN).
d. Waits until the APU is idle and hands off the instruction to the APU.
Table 5-1 lists the minimum-concurrency instructions. The monadic operations, designated
<mop> in Tables 5-1 and 5-4, are listed in Table 5-2. The dyadic operations, designated
<dop> in Tables 5-1 and 5-4, are listed in Table 5-3. Table 5-4 lists the partially-concurrent
instructions, and Table 5-5 lists the fully-concurrent instructions.
The instructions that have external operands and are listed in Tables 5-4 and 5-5 prefetch
the source operand (if no register conflict exists) and release the main processor after the
operand is transferred. When a third instruction is received in the command CIR while the
APU is busy and the CU is either, busy or waiting to hand off its instruction to the APU,
the third instruction must wait. The BIU encodes a null (CA= 1, IA=I) primitive in the
response CIR until the CU becomes idle or hands off its instruction to the APU. Note that
this situation is analogous to the situation in the MC68881 when a second instruction is
received in the command CIR while the APU is still busy with a previous instruction. The
difference is that the MC68881 waits until the APU is available, while the MC68882 waits
until theCU is available.
The conditional instructions listed in Table 5-6 do not allow concurrency. These instructions
are not executed unless both the CU and the APU are idle and all exception flags are
cleared. An extreme case occurs if the MPU writes to the condition CIR of the MC68882
FREESCALE
5-4
MC68881/MC68882 USER'S MANUAL
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