5
Handlers for interrupts, F-line emulation, FTRAPcc instructions, and other exceptions must
not set the EXC-PEND bit in the BIU flag long word, but any exception handler that contains
one or more floating-point instructions must begin with an FSAVE instruction and have
an FRESTORE instruction preceding the RTE instruction. No requirements are imposed on
the floating-point protocol violation exception because it is considered to be a catastrophic
exception from which no recovery is possible.
When a floating-point exception handler that does not begin with an FSAVE instruction
executes in a system that uses an MC68882 coprocessor, one of two things happens. Either
the next MC68882 instruction takes the same exception, producing an infinite loop, or it
takes a protocol violation exception.
When a floating-point exception handler that begins with an FSAVE instruction but does
not set the EXC-PEND bit executes in a system that uses an MC68882 coprocessor, the
next MC68882 instruction takes the same exception, also producing an infinite loop.
When a floating-point exception handler that begins with an FSAVE instruction but does
not end with an FRESTORE instruction is executed in a system that uses an MC68882
coprocessor, a partially-executed instruction following the exceptional instruction may
never be completed. Figure 5-6 shows the required instructions in a minimum exception
handler for an MC68882.
HANDLER FSAVE - (SP) SAVE INTERNAL STATE
MOVE.B {SP),O0 FIRST B~q'E OF STATE FRAME
BEQ NULl. BRANCH IF NULL FRAME
CLR.L DO CLEAR DATA REGISTER
MOVE.B I(SP),DO LOAD STATE FRAME SIZE
BSET #3,(SP, DO) SET BIT 27 OF BIU
NULL FRESTORE (SP)+ RESTORE STATE
RTE RETURN
Figure 5-6. Minimum Exception Handler
An exception handler can access the idle state frame to obtain information about the
exception. The offsets of the exceptional operand, the operand register, and the BIU flags
are different in the MC68881 and the MC68882. In the MC68882, these offsets are greater
than those in the MC68881 by $20. For example, the offset for the exceptional operand is
$08 in the MC68881 and $28 in the MC68882. However, the negative offsets (from the
bottom of the state frame) are the same for both coprocessors. Figure 5-7 shows a code
fragment that can be used to access the exceptional operand and the operand register
image in an exception handler for either coprocessor.
5.2.3 Processing of Special Conditions
The designs of the MPU, the M68000 coprocessor interface, and.the FPCP provide the
performance benefits of concurrent operation while maintaining a conventional sequential
instruction execution model. Processing of special conditions is also performed as if in-
structions were executed sequentially. Refer to the coprocessor interface section of the
appropriate microprocessor user's manual for additional information.
FREESCALE
5-12
MC68881/MC68882 USER'S MANUAL
To Next Page