5
The state frames defined for the null, idle, and busy states of the coprocessor contain all
the information the coprocessor requires to resume operation. Inclusion of the coprocessor
version number in the format word and the checking of that version number during exe-
cution of the FRESTORE instruction prevent restoration of an incompatible context (e.g.,
an MC68881 context in an MC68882).
5.2.3.4 BUS ERRORS. A bus error can occur during initiation of a coprocessor instruction
or while the MPU is accessing memory or CPU address space during execution of a co-
processor instruction. A bus error during initiation of an instruction is used as an indication
that the coprocessor is not present, and the MPU takes an F-line emulator exception. A
bus error during a memory access indicates that some fault (e.g., parity error or page fault)
prevents the memory system from providing the requested operand. The coprocessor
interface, being asynchronous, does not require the MPU to service the bus error exception
at once. No time restrictions on the main processor's response to a bus error exception
exist. After the exception handler has corrected the cause of the bus error, the MPU returns
to the point in the coprocessor instruction dialog at which the fault occurred.
5.2.3.5 EXCEPTION PROCESSING. During the execution of a coprocessor instruction, the
coprocessor releases the main processor after the main processor has completed all the
services the coprocessor requires to execute the instruction. Any exception processing the
main processor performs after being released and before initiation of another coprocessor
instruction has no effect on the coprocessor.
Either the main processor or the coprocessor can detect an exception during execution of
a floating-point instruction. The handlers for these exceptions are bracketed with FSAVE
and FRESTORE instructions as previously described to ensure that coprocessor state in-
formation about concurrently executing instructions is properly restored after execution
of the exception handler completes.
5.2.3.6 SIMULTANEOUS FLOATING-POINT EXCEPTION AND TASK SWITCH INTERRUPT.
Since an interrupt signal can occur at any time, a task switch interrupt can occur simul-
taneously with a floating-point exception detected by the coprocessor. The FPCP and the
coprocessor interface with the MPU are designed to preserve the sequential instruction
execution model in this case. Figure 5-8 shows an FMUL instruction executing in an MC68882,
followed by an FADD instruction. A task switch interrupt occurs as the main processor
responds to the exception. The sequence of events is as follows:
1. The MC68882 is executing the two instructions concurrently.
2. The FMUL instruction is executing in the APU, the CU has performed the conversion
of the source operand, and the CU is waiting to hand off the FADD instruction when
the APU becomes idle. The MC68882 is returning null (CA=0, IA=0) primitives to
synchronize the main processor. The main processor is reading the primitives, re-
sponding to any pending interrupts.
3. The FMUL instruction detects an exception, which is reported by the FADD instruction
with a take mid-instruction exception primitive.
4. The main processor recognizes a pending interrupt as it reads the take mid-instruction
exception primitive. Because of the internal timing, however, the MPU processes the
floating-point exception first.
FREESCALE
5-14
MC68881/MC68882 USER'S MANUAL
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