mode and reads the response CIR to determine if the previous coprocessor instruction is
completed. In this manner, the exception processing for the interrupt is completely trans-
parent to the handling of the trace exception by the MPU and FPCP pair.
If an interrupt handler for a system using an FPCP requires the use of the FPCP, or if a task
switch requires that the context besaved, an FSAVE instruction should be the first floating-
point instruction executed by the routine. To restore the original context, an FRESTORE
must be executed by the routine before the RTE instruction. If an interrupt handler does
not interact with the FPCP, no context save operations are required.
Many FPCP instructions require a fairly long time to execute, and the MPU may be forced
to wait until the FPCP execution is complete before proceeding to the next instruction
(either because the instruction does not allow concurrency or the main processor is in the
trace mode). Normally, the MPU can only process pending interrupts when it reaches an
instruction boundary, but this might adversely affect interrupt latency if it is not allowed
to process interrupts while waiting on the FPCP. To reduce interrupt latency as much as
possible, the FPCP always sets the interrupts allowed (IA) bit in the null (CA= 1) and null
(CA =0, PF = 0) primitives; thus allowing interrupts to be processed while the MPU is waiting
for the coprocessor to complete an operation. In fact, most FPCP instructions, regardless
of their overall execution time, provide for very small interrupt latency times. The worst-
case interrupt latency instruction for the FPCP is the FRESTORE with a busy state frame
(see 8.3 INTERRUPT LATENCY TIMES for more information).
6.2.6 Address and Bus Errors
Bus cycle faults may occur while processing FPCP instructions during the MPU accesses
of the coprocessor interface registers, or during memory cycles run by the MPU to access
instructions or data. If the MPU receives a fault while running the bus cycle which initiates
an FPCP instruction (i.e., the initial write to the command or condition CIR), it assumes
that no FPCP is present in the system, and takes a pre-instruction exception using the
F-line emulator vector number. Thus, an MPU system may utilize software emulation of
the FPCP or provide hardware floating point, and the actual configuration is transparent
to the application program. If any other access to the FPCP is faulted, it is assumed that
the coprocessor has failed, and the MPU takes a bus error exception.
If the MPU has a memory fault while executing an FPCP instruction, it takes an address
error or bus error exception. After the fault handler corrects the fault condition, it may
return and communication with the FPCP continues as if the fault had not occurred.
6.2.7 Privilege Violations
The MPU operates at one of two privilege levels: the user level or the supervisor level.
The privilege level determines which operations are legal, and the S bit in the MPU status
register determines the privilege level. Most programs execute at the user level where
accesses are controlled, and effects on other parts of the system are limited. The operating
system executes at the supervisor level, has access to all resources, and may execute all
instructions; hence, it performs the overhead tasks for the user-level programs.
The FPCP FSAVE and FRESTORE instructions are privileged instructions; all others are
nonprivileged. An attempt to execute the FSAVE or FRESTORE instructions while at the
MC66661/MC66662 USER'S MANUAL
FREESCALE
6-27
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