6.4.1 FSAVE and FRESTORE Instruction Overviews
The basic mechanism for performing a context switch on the FPCP is provided by the
FSAVE and FRESTORE instructions. These instructions arG a logical extension to the in-
struction continuation mechanism that is used by the MC68010, MC68020, and MC68030
processors to support virtual memory. The FSAVE instruction is treated much like a
microcode-level interrupt to the FPCP, instructing it to suspend any operation that is being
executed (at the earliest possible boundary) and make a complete copy of the internal state
of the machine into memory. This is similar to the effect of the assertion of bus error to
the main processor. To restore the internal state saved by the FSAVE instruction, the
FRESTORE instruction is used, which is similar to the RTE instruction on the main processor.
The internal state information that is stored in memory by the FSAVE instruction contains
the image of the flags and registers not visible to the user, including the address in the
microprogram counter, temporary register values, and pending exception information.
After the execution of an FSAVE, the FPCP enters the idle state, and any pending exceptions
are cleared. To perform a complete context save, FMOVEM instructions must be used to
save the user-visible portion of the machine; and then a new context may be loaded. When
it is necessary to reload the context that was previously saved, these steps are reversed:
first, the FMOVEM instructions load the user-visible context, followed by an FRESTORE
instruction, which loads the nonuser-visible context. After the execution of the FRESTORE,
the FPCP returns to the exact context that existed just before the FSAVE instruction was
executed, and execution continues from that point.
Depending on the state of the FPCP when an FSAVE instruction is executed, the format of
the internal state information written to memory may be in one of three forms: idle, null,
or busy. Also, the FPCP may force the MPU to wait for a short time while the internal state
is prepared for the save operation. During execution of an FRESTORE instruction, the FPCP
interprets the state information read from memory (and written to the restore CIR) to
determine the appropriate response action. The FRESTORE is destructive in that the FPCP
immediately stops any operation that it may be performing and begins to load the next
context; thus there is no need for a mechanism in the FRESTORE instruction to allow the
FPCP to make any service requests to the MPU. The protocol of the FSAVE and FRESTORE
instructions is described in detail in a subsequent paragraph.
6.4.2 State Frames
The three state frame formats that are generated by the MC68881 are shown in Figure
6-4. In all three state frames, the first long word of the frame has the same format. The
least significant word of this long word is reserved for future definition by Freescale; it is
included to allow long word alignment of a state frame in memory. The most significant
word of the first long word (called the format word) contains the version number of the
coprocessor that generated the state frame (in the most significant byte) and the size of
the internal state stored in the frame (in the least significant byte). For the null state frame,
the size value is undefined. Although the version number and frame size values are defined
by the MC68881, the M68000 Family coprocessor interface defines the null format word
which is the one format word value that must be recognized by any coprocessor as de-
scribed in a subsequent paragraph.
Two of the state frame formats for the MC68882, shown in Figure 6-5, differ from the
corresponding state frames for the MC68881 in two respects. First, the idle and busy state
MC66661/MC66662 USER'S MANUAL FREESCALE
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