6
Bit 27 This bit indicates that a floating-point exception is pending, which is
reported when the MPU attempts to initiate the next floating-point in-
struction (after a FRESTORE of this state frame). If this bit is zero, an
exception is pending, and the logical AND of the FPSR EXC and FPCR
ENABLE bytes indicates the type of the pending exception. This bit may
be read by an exception handler (particularly a trace routine) to deter-
mine the exception status of the FPCP. As described in a subsequent
paragraph, a user program can modify this bit and the FPSR EXC and
FPCR ENABLE byte images to create a software generated pending
exception.
NOTE
This bit must be set by the exception handler immediately before an
FRESTORE and RTE instruction. When this bit is not set in the exception
handler, the MC68882 re-executes the handler.
Bit 28
This bit indicates that the FPCP is expecting the next coprocessor inter-
face register access to be to the operand CIR. This bit is used by the BIU
as part of the protocol violation checking hardware and should not be
modified. If this bit is a zero, an access of the operand CIR is pending,
and the state of bit 29 determines whether the expected access is a read
or write cycle. Bits 28-30 combine to define the pending operation as
listed in Table 6-4.
Bit 29
Bit 30
This bit defines the type of pending operand access that is expected or
the type of pending operation that is saved in the command~'condition
register image. This bit should not be modified. Bits 28-30 combine to
define the pending operation as listed in Table 6-4.
This bit indicates that the FPCP has received a new command word or
conditional predicate from the MPU, but has not been able to begin
execution of that operation. If this bit is zero, the command word or
conditional predicate that was received is contained in the command;
condition register images of the state frame. This bit should not be
modified. Bits 28-30 combine to define the pending operation as listed
in Table 6-4.
Bit 31
This bit indicates that a protocol violation has been detected by the FPCP,
and the MPU has not responded with an exception acknowledge or abort
operation. If this bit is a one, a protocol violation is pending. This bit
should not be modified.
NOTE
The formats of the idle state frame and the BIU flags shown are for the initial
production versions of the FPCP; this format is identified by the format word
values ($1F18 and $3F18 for the MC68881, and $1F38 for the MC68882). Freescale
reserves the right to utilize different state frame formats and format word values
to support future revisions to the FPCP.
FREESCALE
6-34
MC68881/MC68882 USER'S MANUAL
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