6
6.4.3.2 IDLE PHASE. In this phase, the FPCP is not executing an instruction, but at least
one instruction has been executed since the last hardware reset or FRESTORE of a null
state frame. When the MC68881 is in this state and an FSAVE is executed, an idle format
word is returned immediately, and an idle state frame is stored.
6.4.3.3 INITIAL PHASE. In this phase, the FPCP is acquiring instruction and operand words
from the MPU. In a virtual memory system, a memory fault can occur during this phase
due to an attempt to access an operand that is not resident in main memory. In this case,
the MPU traps to a fault handler to initiate a transfer from secondary storage, typically
involving one or more disk accesses. After initiating the transfer, the operating system
usually switches the main processor and coprocessor(s) to another program, thus neces-
sitating a save of the coprocessor state and restoration of the state of the coprocessor
relative to the next program. To facilitate saving and restoring the coprocessor, the FPCP
responds immediately to a save command during the initial phase by storing a busy state
frame.
6.4.3.4 MIDDLE PHASE. The middle phase occurs only in FPCP instructions that take
significant processing time (i.e., remainder, transcendental functions, and BCD conver-
sions). During this phase, the internal microcode sequence of the FPCP provides for periodic
checkpoints to determine if the MPU has issued a save command. If the MPU initiates a
save command to the FPCP between check points, the FPCP sets an internal flag to denote
the receipt of the command and returns a come-again format word to the MPU. The MPU
repeatedly reads the save CIR until it receives a valid format word. The FPCP continues
internal processing up to the next checkpoint, at which time processing stops, and the next
read of the save CIR acquires the appropriate format word to start the save operation. At
this point, the save command proceeds to completion, and the FPCP supplies a busy state
frame.
6.4.3.5 END PHASE. This phase begins when the FPCP is almost finished with a long
instruction. The length of the end phase is approximately equal to the amount of time
required to perform a save of a busy state frame. When the FPCP reaches the end phase,
it takes less time to complete execution of the instruction and save an idle frame than to
immediately save a busy state. During this phase, the FPCP uses the come-again format
word to force the MPU to wait for the completion of the instruction, and then saves an
idle state frame.
Note that most of the FPCP instructions proceed directly from the initial phase to the end
phase, and thus, most state frames generated by the FPCP are idle frames.
6.4.4 FRESTORE
Protocol
When the MPU decodes an FRESTORE instruction, it evaluates the effective address to
locate the format word for the state frame, and writes that format word to the restore CIR
of the FPCP. In response to this write cycle, the FPCP aborts any operation that may be in
progress and prepares to load a new internal state. The format word that is written to the
restore CIR is checked for validity (it must be a null, idle, or busy format word with a version
number that matches that of the specified device) before the restore operation begins.
After the MPU writes the format word to the FPCP, it then reads the restore CIR to verify
FREESCALE
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MC68881/MC68882 USER'S MANUAL
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