data format, since additional format information is required to generate a packed decimal
destination operand when a dynamic k factor is specified. If the destination data type is
packed decimal and a dynamic k factor is used, the first response is the transfer single
main processor register primitive (to transfer the contents of the register containing the k
factor). For all other destination data formats, the first request is the null (CA = 1 ) primitive,
since a conversion from the internal data format to the desired destination format must
be performed before any further action is required of the main processor. For the dynamic
k-factor case, the conversion starts after the main processor register transfer is completed.
The conversion starts immediately after the first read of the response CIR for all other
destination operand formats. The main processor is allowed to service pending interrupts
while it is waiting for the conversion to complete.
If any arithmetic exceptions are enabled, the first primitive requests the transfer of the
program counter. However, this request can be ignored when the main processor uses an
MC68881 ; the MC68882 issues a protocol violation when the main processor ignores this
request. The program counter write cycle may not affect instruction execution time (since
it can occur concurrently with the operand conversion if the destination format is not packed
decimal with a dynamic k factor). Only the first primitive requests the transfer of the
program counter; thus, if the transfer single main processor register primitive is issued
first, the PC bit is not set in any subsequent null primitive. If the first primitive is the null
primitive and the program counter transfer is required, the PC bit is set.
The pass program counter operation is requested in one of two of the primitive encodings
(shown in Figure 7-20 with the notation
"PC=x"). For the packed decimal with a dynamic
k-factor case, the dark shaded operations are always performed with the PC bit set if
necessary. The MPU services the transfer single main processor primitive with the PC bit
set by first transferring the program counter and then transferring the requested register.
For all other destination data formats, the dark shaded operations are not performed, and
the box labeled "Convert" is "folded under" the first box labeled "Read Response". For
these cases, the null primitive may request the transfer of the PC, and that transfer occurs
concurrently with the operand conversion by the FPCP.
When the operand conversion is completed, the next read of the response CIR returns the
evaluate effective address and transfer data primitive. The main processor then reads the
conversion result from the operand CIR and writes it to the appropriate destination location.
Note that the read of the evaluate effective address and transfer data primitive causes the
response CIR encoding to be changed to the null primitive, thus avoiding spurious request
primitives in non-MC68020 or non-MC68030 based systems.
The operation boxes that are marked
"R" or "W" indicate an operand read or write cycle,
respectively, by the MPU. Those operand transfer boxes that are lightly shaded are op-
tionally executed, depending on the size and location of the source operand. For example,
none of the shaded boxes are executed for destination operands that reside in the MPU
registers.
The MC68882 dialog differs from the dialog shown in Figure 7-20 when the operand data
format is single, double, or extended, except for the following conditions:
• The data in the floating-point register is data type NAN, unnormalized, or denormalized.
• A rounding overflow or underflow has occurred, and the operand data format is single
or double.
• The INEX2 bit of the FPSR exception enable byte is set, and the operand data format
is single or double.
MC68881/MC68882 USER'S MANUAL FREESCALE
7-25
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