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When the MPU polls the response CIR, the MC68881 begins execution of the instruction
in the fourth clock cycle of the read cycle. As the MC68881 proceeds with the conversion
operation, the MPU then completes the cpGEN start-up operation and processes the null
(CA=0) primitive. The 10 clock cycles required to perform these operations overlap with
the execution of the instruction by the MC68881 and, thus, are not included in the overall
execution time calculation (although they are included in the effective execution time
calculation). The same consideration applies to the second and third diagrams in Figure
8-4.
As shown in the second diagram of Figure 8-4, if the first word of the instruction is at an
odd word address, the prefetch requested by the cpGEN start-up is filled from the temporary
register (which was loaded by a prefetch requested during the previous MPU instruction)
and an external bus cycle is not required. When the null (CA=0) primitive is processed, a
second prefetch request is generated which must be filled by the execution of an external
bus cycle. Thus, the start-up operation for this case is a minimum of three clock cycles
shorter than the first case (although the overlap allowed time is also shorter) while the
time required to process the null primitive is at least one clock cycle longer. Since the null
processing overlaps with the execution of the operand conversion by the MC68881, the
overall execution time for the instruction is shorter, although the overlap allowed time at
the end of the instruction is reduced.
For the third case, both of the instruction prefetch requests generated during the instruction
execution are satisfied by either the temporary register or the on-chip instruction cache.
Thus, the overall execution time achieves the absolute best case while allowing the max-
imum possible overlap between the two devices.
The diagram in Figure 8-5 illustrates the execution of the FMOVE.S (An),FPn instruction
where the instruction is even-word aligned, the MPU cache is disabled, and at least one
of the arithmetic exceptions is enabled. Under these conditions, the cpGEN start-up op-
eration is identical to the first diagram in Figure 8-4, except that the primitive returned by
the MC68881 is evaluate effective address and transfer data with the PC and CA bits set.
Thus, the first operation performed by the MPU while processing this primitive is to pass
the program counter, which adds two clock cycles to both the effective and overall execution
times. (Note that the third clock cycle of the coprocessor write cycle overlaps with the
effective address calculation.) The MPU then evaluates the effective address, (An), which
requires two clock cycles, and transfers the 32-bit single precision operand from memory.
The come-again operation is then performed, which requires 10 clock cycles, followed by
a four clock period during which the null (CA=0) primitive is processed.
The MC68881 does not start the input conversion operation until the single precision
operand is internally passed to the execution unit. The MC68881 bus interface unit requires
three clocks from the end of the operand write cycle to transfer the operand to the execution
unit; thus, the conversion does not begin until three clock cycles after the end of the write
cycle. This three-clock-cycle transfer operation and part of the conversion operation occur
simultaneously with the completion of the CA= 1 and null processing by the MPU. Thus,
15 clock cycles of the MPU effective execution time do not contribute to the overall exe-
cution time for the instruction.
The previous four examples are intended to clarify the meaning of the detailed execution
timing tables that follow. The only difference between the FMOVE instruction examples
presented and any of the monadic or dyadic instructions is that the convert and calculate
times are different. (The round time is also different if an exception occurs.) Also, the
FREESCALE
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MC68881/MC68882 USER'S MANUAL
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