FDIV Divide FSGLDIV Single Precision Divide
FMOD Modulo Remainder FSGLMUL Single Precision Multiply
FMUL Multiply FSUB Subtract
Assuming that operands are single precision, the FSGLMUL and FSGLDIV instructions
round results as such while maintaining the range of extended precision. In special
applications where multiply and divide performance are more important than loss of pre-
cision, the FSGLMUL and FSGLDIV instructions can be used.
1.4.5 Branch, Set, and Trap-On Condition
The floating-point branch, set, and trap-on condition instructions implemented by the FPCP
are similar to the equivalent integer instructions of the M68000 Family processors, except
more conditions exist due to the special values in IEEE floating-point arithmetic. When a
conditional instruction is executed, the FPCP performs the necessary condition checking
and reports the result, true or false, to the MPU; the MPU then takes the appropriate action.
Since the FPCP and MPU are closely coupled, the floating-point branch operations are
quickly executed.
The FPCP conditional operations are:
FBcc Branch
FDBcc Decrement and Branch
FScc Set According to Condition
FTRAPcc Trap-on Condition (with an Optional Parameter)
where:
cc is one of the 32 floating-point conditional test specifiers listed in 3.3 PACKED DECIMAL
REAL DATA FORMAT.
1.4.6 Miscellaneous Instructions
Miscellaneous instructions include moves to and from the status, control, and instruction
address registers. Also included are the virtual memory/machine FSAVE and FRESTORE
instructions that save and restore the internal state of the FPCP.
FMOVE <ea>,FPcr Move to Control Register(s)
FMOVE FPcr,<ea> Move from Control Register(s)
FSAVE <ea> Virtual Machine State Save
FRESTORE <ea> Virtual Machine State Restore
1.5 ADDRESSING MODES
The FPCP does not perform address calculations. Thus, when the FPCP instructs the MPU
to transfer an operand via the coprocessor interface, the MPU performs the addressing
mode calculations requested in the instruction. In this case, the instruction is encoded
specifically for the MPU, and the instruction execution by the FPCP is dependent only on
the value of the command word written to the FPCP by the main processor.
This interface is quite flexible and allows any addressing mode to be used with floating-
point instructions. For the M68000 Family, these addressing modes include immediate,
postincrement, predecrement, data or address register direct, and the indexed/indirect
MC68881/MC68882 USER'S MANUAL FREESCALE
1-15
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