--p--
Power Considerations, 12-1
Power Supply Connections, 9-5
Pre-lnstruction Exception
Dialog, 7-31
MC68882, 7-33, 7-34
Primitive, 7-18
Format, 7-18
Stack Frame, 7-18
Predicates, Conditional,
4-136
Primitive,
Coprocessor Response, 7-10
Evaluate Effective Address and Transfer Data, 7-13
Null, 7-11
Take Mid-Instruction Exception, 7-18
Take Preolnstruction Exception, 7-17
Transfer Multiple Coprocessor Registers, 7-15
Transfer Single Main Processor Register, 7-14
Privilege Violation Exception, 6.27
Processing,
Bus
Arbitration, 5-13
Error, 5-14
Condition Code, 4-16
Context Switch, 5-13, 5-14
Exception, 5-14, 6-1
Interrupt, 5-13
Overflow, 4-16
Round, 4-16
Underflow, 4-16
Program Control Instructions, 4-4
Programming,
Coprocessor
Applications, 5-1
Systems, 5-10
Considerations, 1-16
Model, 1-4, 2-1
Protocol,
FRESTORE Instruction, 6-38
FSAVE
~nstruction,
6-36
Instruction, 7-9
Restrictions, Coprocessor Interface, 10-15
Violation Exception,
Coprocessor-Detected, 6-20
MPU.Detected, 6-25
Q
Quotient Byte, 1-5, 2-6
R
RNV Signal, 9-3, 10-6, 10-12
Ratings, Maximum, 12-1
Read Cycles,
Asynchronous, 10-12
Synchronous, 10-9, 10-10
ReadNVrite Signal, 9-3, 10-6, 10.12
Recovery, Exception, 6-22
Register,
Conflicts, MC68882, 5-9
Coprocessor Interface, 1-8, 7-2, 7-3, 9~2,
10-1
Floating-Point
Control, 2-2, 2-3, 6-4, 6-18, 10-5
Data, 2-1
Field Encoding, 4-127
Instruction Address, 2-8, 6.22, 7-7, 7-27, 7-28,
7-35
Status, 2-4-2-7, 6-4, 6-19, 10-5
FPIAR, 2-8, 6.23, 7-8, 7-27, 7-29, 7-39
Register Select CIR, 6-21, 7-7, 7-15, 7-27, 10-3,
10-14
Register-to-External Instructions, 4-129
Dialog,
7-24
MC68882, 7-26
Format, 4-129
Register-to-Register Instructions, 4-127
Dialog, 7-22, 7-23
Format, 4-127
Register/Memory Field, 4-138
Reset
Logic Example, 10-6
Operation, 10.5
Phase, 6-37
RESET Signal, 9-4, 10-5
Response CIR, 5-1, 5-2, 5-4, 5-8, 5-13, 6.3, 6.5, 6.10,
6-14, 6.17, 6-20-6-22, 5-25, 6-35,
6.37, 7-3-7-6, 7-10, 7-19, 7-31,
8-7-8-11, 8-24, " 8-25, 8-33, 8-36,
10-9, 10-12, 10-14, 10-15
Response Primitive,
Coprocessor, 7-10
Format, 7-10
Summary, 7-19
Responses, Save Command, 6-36
Restore CIR, 6-21, 6-38, 7-5, 7-6, 7-30, 10.13
Restrictions,
Coprocessor Interface Protocol, 10-15
Inter-Cycle Timing, 10-14
• Round Processing, 4-16
Round/Store Result Phase Timing, 8-4
Rounding
Algorithm, 5-17
Modes, 6.15
Operation Times, 8-35
S
S Format, 3-10
Save CIR, 6-21, 6-35-6-37, 7-5-7-7, 7-17, 7-29,
7-40, 8-18, 10-9, 10-14, 10-15
Save Command Responses, 6-35
ScanPC, 7-19
Sense Device
Circuit Example, 9-5
Signal, 9-5
FREESCALE
INDEX-8
MC68881/MC68882 USER'S MANUAL
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