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2.4 FLOATING-POINT INSTRUCTION ADDRESS REGISTER
A majority of the FPCP instructions operate concurrently with the MC68020/MC68030 (MPU).
That is, the MPU
can be executing instructions while the FPCP is simultaneously executing
a floating-point instruction. Additionally, the MC68882 can execute two floating-point in-
structions concurrently. As a result of this
nonsequential instruction execution, the program
counter value stacked by the MPU, in response to an enabled floating-point exception trap
may not point to the offending instruction.
For the subset of the FPCP instructions that generate floating-point exception traps, the
32-bit floating-point instruction address (FPIAR) register is loaded with the logical address
of an instruction before the instruction is executed (unless all arithmetic exceptions are
disabled). This address can then be used by a floating-point exception handler to locate a
floating-point instruction that has caused an exception. Since the FPCP FMOVE to/from the
FPCR, FPSR, or FPIAR and FMOVEM instructions cannot generate floating-point exceptions,
these instructions do not modify the FPIAR. These instructions can be used to read the
FPIAR in the trap handler without changing the previous value.
This register is cleared by the reset operation or a restore operation of the null state.
FREESCALE
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MC68881/MC68882 USER'S MANUAL
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