4
FDBcc Test Condition, Decrement, and Branch FDBcc
Operation:
If condition true then no operation
else Dn -1 I) Dn
if Dn =~
- 1
then PC+d j PC
else execute next instruction
Assembler
Syntax:
FDBcc Dn,<label>
Attributes:
Unsized
Description:
This instruction is a looping primitive of three parameters: a floating-point
condition, a counter (an MPU data register) and a 16-bit displacement. The FPCP first
tests the condition to determine if the termination condition for the loop has been
met, and if so, the main processor proceeds to execute the next instruction in the
instruction stream. If the termination condition is not true, the low order 16-bits of the
counter register are decremented by one. If the result is - 1, the count is exhausted,
and execution continues with the next instruction. If the result is not equal to - 1,
execution continues at the location specified by the current value of the PC plus the
sign-extended 16-bit displacement. The value of the PC used in the branch address
calculation is the address of the displacement word.
The conditional specifier cc selects any one of the 32 floating-point conditional tests
as described in 4.4 CONDITIONAL TEST DEFINITIONS.
Status Register;
Condition Codes:
Quotient Byte:
Exception Byte:
Accrued Exception Byte:
Not affected
Not affected
BSUN Set if the NAN condition code is set and the
condition selected is an IEEE nonaware test
SNAN Not Affected
OPERR Not Affected
OVFL Not Affected
UNFL Not Affected
DZ Not Affected
INEX2 Not Affected
INEX1 Not Affected
The lOP bit is set if the BSUN bit is set in the exception byte.
No other bit is affected.
FREESCALE
4-38
MC68881/MC68882 USER'S MANUAL
To Next Page
Loading...