15 14 13 12 11 10 9 8 7 6 5
, I, I, ]~ I CO'ROC~S~DR'O
I0 I' I0
I
16~BIT DISPLACEMENT
4 3 2 1
CONDITIONAL PREDICATE
15 14 13 12 tl 10 9 8 7 6 5
' I' I' I' ] COPROCESSOR ,D
I0 {'
I' I
32-BIT DISPLACEMENT
4 3 2 1
CONDITIONAL PREDICATE
The conditional predicate field specifies the conditional test to be performed. Table 4-20
lists the conditional predicate encodings and the FPCP responses, For details of the re-
sponse calculation, refer to 4.4 CONDITIONAL TEST DEFINITIONS.
The displacement is a twos-complement integer that indicates the relative distance in bytes
from the displacement word(s) (i.e., the PC value used in the branch destination calculation
is the address of the displacement word(s)). A 16-bit displacement is sign extended before
it is used in the branch destination calculation.
NOTE
From the
perspective
of the FPCP, the two forms of this instruction are identical.
The size of the displacement is determined by the MPU and is transparent to the
FPCP. Also, the FNOP instruction syntax that is recognized by Freescale assem-
blers generates an FBcc.W instruction with cc = F (false) and a displacement value
of zero.
4.7.4 Save Instruction Format
The FSAVE instruction indicates that the FPCP must immediately suspend any current
operation and save the internal state in memory. Effective addressing modes are restricted
to control alterable and address register indirect with predecrement modes. The encoding
format for this instruction is:
15 14 13 12 11 10 9 8 7 6
1 1 1 1 ID t O 0
5 4 3 2 1 0
EFFECTIVE ADDRESS
MODE I REGISTER
4.7.5 Restore Instruction Format
\
The FPCP restore instruction indicates that regardless of the current state of operation, a
new internal state is to be loaded immediately. Effective addressing modes are
restricted
to control and address register indirect with
postincrement
modes. The encoding format
for this instruction is:
15 14 13 12 11 10 9 8 7 6
[ I
I, 1 o I, I
1 1 1 1 ID
5 4 3 2 1 0
EFFECTIV~ ADDRESS
MODE | REGISTER
MC68881/MC68882 USER'S MANUAL
FREESCALE
4-137
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