In addition to these features, the MC68882 provides:
• Concurrent execution of multiple floating-point instructions.
• Special-purpose hardware for high-speed conversion of binary real memory operands
to/from the internal extended format.
• Simultaneous access to the floating-point registers by the MC68882's conversion and
arithmetic processing units.
• Reduced coprocessor interface overhead to increase throughput.
1.1 THE COPROCESSOR CONCEPT
The FPCP functions as a coprocessor in systems where the MC68020 or MC68030 is the
main processor via the M68000 coprocessor interface. It functions as a peripheral processor
in systems where the main processor is the MC68000, MC68008, or MC68010.
The FPCP utilizes the M68000 Family coprocessor interface to provide a logical extension
of the MPU registers and instruction set in a manner that is transparent to the programmer.
The programmer perceives the MPU and FPCP execution model as if both devices were
implemented on one chip.
A fundamental goal of the M68000 Family coprocessor interface is to provide the pro-
grammer with an execution model based upon sequential instruction execution by the
MPU and the FPCP. For optimum performance, however, the coprocessor interface allows
floating-point instructions to execute concurrently with MPU integer instructions. Concur-
rent instruction execution is further extended by the MC68882, which can execute multiple
floating-point instructions simultaneously. However, the coprocessor interface and the
FPCP are designed to maintain a strictly sequential instruction execution model from the
programmer's viewpoint.
The FPCP is a non-DMA type coprocessor that uses a subset of the general-purpose co-
processor interface supported by the MPU. Features of the interface implemented in the
FPCP are as follows:
• The main processor and the FPCP communicate via standard M68000 bus cycles.
• Communication between the main processor and the FPCP is not dependent upon the
architecture of the individual devices (e.g., instruction pipes or caches, addressing
modes).
• The main processor and the FPCP can operate at different clock speeds.
• The FPCP instructions support all addressing modes provided by the main processor.
• All effective addresses calculations and data transfers performed by the main processor
at the request of the coprocessor.
• Overlapped (concurrent) instruction execution enhances throughput while maintaining
the programmer's model of sequential instruction execution.
• Coprocessor detection of an exception that requires a trap to be taken is serviced by
the main processor at the request of the FPCP.
• Support of virtual memory/virtual machine systems is provided via the FSAVE and
FRESTORE instructions.
FREESCALE
1-2
MC68881/MC68882 USER'S MANUAL
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