• Up to eight coprocessors can reside in a system simultaneously.
• Multiple coprocessors of the same type are allowed.
• Systems can use software emulation of the FPCP without reassembling or relinking
user software.
1.2 HARDWARE OVERVIEW
The MC68881 and MC68882 are high-performance floating-point devices designed to in-
terface with the MC68020 or MC68030 as coprocessors. These coprocessors fully support
the MPU virtual machine architecture and are implemented in HCMOS, Freescale's low-
power, small-geometry process. This process allows CMOS and HMOS (high-density NMOS)
gates to be combined on the same device. CMOS structures ere used where speed and
low power are required, and HMOS structures are used where minimum silicon area is
desired. As a result, HCMOS technology provides the combined advantages of high-per-
formance and low-power consumption without enlarging the die size.
In systems using the MC68000, MC68008, or MC68010 as the main processor, the MC68881
or MC68882 functions as a peripheral processor. The configuration of the FPCP as a peripheral
processor or coprocessor can be completely transparent to user software (i.e., the same
object code can be executed in either configuration).
,The architecture of the FPCP appears to the user as a logical extension of the M68000
Family architecture. Because of the coupling of the coprocessor interface~ the MPU pro-
grammer can view the FPCP registers as though the registers were resident in the MPU.
Thus, an MPU and FPCP device pair appears to be one processor that supports seven
floating-point and integer data types with eight integer data registers, eight address reg-
isters, and eight floating-point data registers.
The FPCP programming model is shown in Figures 1-1 through 1-6 and consists of the
following:
• Eight 80-bit floating-point data registers (FP7-FP0). These registers are analogous to
the integer
data
registers (D7-D0) and are completely general purpose (i.e., any in-
struction may use any register).
• A
32-bit control register that contains enable bits for each class of exception trap, and
mode bits to set the user-selectable rounding and precision modes.
• A
32-bit status register that contains floating-point condition codes, quotient bits, and
exception status information.
• A
32-bit instruction address register that contains the main processor memory address
(virtual) of the last floating-point instruction that was executed. This address is used
in exception handling to locate the instruction that caused the exception.
The connection between the MPU and the FPCP is a simple extension of the M68000 bus
interface. The FPCP is connected as a coprocessor to the MPU, and a chip-select signal
(decoded from the MPU function codes and address bus)selects the FPCP. Figure 1-7
illustrates the coprocessor/MPU configuration.
As shown in Figure 1-8, the MC68881 is internally divided into two processing elements;
the bus interface unit (BIU) and the arithmetic processing unit (APU). The BIU communicates
MC68881/MC68882 USER'S MANUAL
FREESCALE
1-3
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