6
3. The beginning of the instruction immediately following the instruction that caused or
detected the exception (post-instruction exception}. Note that neither the MC68881
nor the MC68882 reports the post-instruction exception.
The following paragraphs describe the causes of various coprocessor-related exceptions
and how they are handled by the FPCP and the main processor. Throughout this discussion,
the main processor is assumed to be an MC68020 or MC68030, although any other pro-
cessor can be programmed to emulate the M68000 Family coprocessor interface that is
implemented on the MPU.
6.1 COPROCESSOR-DETECTED EXCEPTIONS
Coprocessor-detected exceptions fall into two categories: those related to communications
with the main processor (F-line traps and protocol violations} and those related to the
execution of floating-point instructions (computational errors such as divide by zero, or
instructions designed to cause a trap such as the FTRAPcc instruction). The protocol for
handling each of these exception types is
described in detail in this section.
The main processor coordinates all exception processing. Therefore, when the FPCP detects
an exception, it cannot always force exception processing immediately but must wait until
the main processor is ready to start exception processing. The main processor is always
prepared to process an exception whenever it reads the response coprocessor interface
register (CIR). For the MC68881 and, in most cases, for the MC68882, if a coprocessor-
detected exception occurs during the
calculation phase of an instruction, it is held pending
within the FPCP until the next write to the command or condition coprocessor inted'ace
register (CIR). Then, instead of returning the first primitive of the dialog for the new in-
struction, the FPCP returns the take pre-instruction exception primitive to start exception
processing for the offending instruction. (For the MC68881, the offending instruction is
always the previous floating-point instruction, since no multiple floating-point concurrency
is allowed; for the MC68882, the offending instruction may not necessarily be the previous
instruction.)
The FPCP may also report an exception after writing an operand to memory. In this case,
a take mid-instruction exception primitive is issued after the operand is stored in memory
(if a conversion error occurred). The mid-instruction exception allows the exception handler
to more easily determine the address of the exceptional operand, since the MC68020
includes the results of the effective address calculation for the destination operand in the
mid-instruction stack frame (the long word at offset +$10).
It is possible for the MC68882 to report a mid-instruction exception as a result of an
exception created by a previous instruction. This occurs when the instruction in the APU
reports an exception while a second instruction in the conversion unit (CU) is waiting to
be handed off to the arithmetic processing unit (APU). Consider the case of two FMUL
instructions:
FMUL.X FP0,FP1 (which results in an
exception)
FMUL.B <ea>,FP2
At the time the second FMUL instruction is initiated, the first FMUL instruction is still
executing in the APU. The CU instructs the bus interface unit (BIU) to fetch the program
counter, and prefetch the byte operand. Since the CU cannot convert the byte operand, it
instructs the BIU to encode a null (CA= I, IA= 1) in the response CIR, and waits to hand
FREESCALE
6-2
MC68881/MC68882 USER'S MANUAL
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