off the instruction to the APU. When the first FMUL instruction finally finishes in the APU
and reports an exception, the second FMUL instruction is in the middle of the instruction,
hence a take mid-instruction exception is taken. Note that in this case, the destination
operand is a floating-point register, and therefore the effective address calculation for the
destination operand in the mid-instruction stack frame of the MPU is undefined.
The third point at which the FPCP can indicate an exception to the main processor is in
response to a protocol violation. If an unexpected access to a coprocessor interface register
causes a protocol violation, the FPCP immediately encodes the response CIR to the take
mid-instruction exception primitive with the protocol violation vector number, This allows
the protocol violation handler to determine the cause of the violation (either an illegal
primitive from the FPCP or an illegal access by the MPU) and perform necessary action.
Since an FPCP protocol violation is a catastrophic error, and the FPCP cannot return an
illegal primitive, the only appropriate action is to abort the task that detected the protocol
violation.
The basic protocol followed in response to a coprocessor-detected exception is:
1. The FPCP encodes the appropriate take exception primitive (pre- or mid-instruction),
along with the vector number, in the response CIR.
2. The MPU reads the response CIR (usually in an attempt to initiate the next instruction)
and receives the take exception request.
3. The MPU acknowledges the request by writing an exception acknowledge to the
control CIR. The appropriate stack frame is then stored in memory, and control is
transferred to the exception handler routine.
4. The response to the exception acknowledge differs for the type of exception and for
the FPCP, as follows:
a. Protocol violation:
MC68881 -- Aborts all internal operations that may be active and enters the
idle state.
MC68882 -- Same as MC68881.
b. BSUN and F-line (detected by the coprocessor):
MC68881 -- Clears the exception and enters the idle state.
MC68882 -- Same as MC68881.
c. Arithmetic (Operr, Overflow, Underflow, Divide by zero, Inexact result):
MC68881 -- Clears the exception and enters the idle state.
MC68882 ~ Refer to 5.2.2 Exception Handler Code.
The following paragraphs discuss the exception vector assignments used by the FPCP,
and each of the exception types thatcan be detected by the FPCP.
The M68000 Family of processors uses a data structure called the exception vector table
as a localized dispatching point for all exceptional conditions that may occur in a system.
The exception vector table is a 1024-byte structure made up of 256 long word entries. Each
entry in the table is a pointer to the routine that services a specific exceptional occurrence.
When an exception occurs, the processor supplies an index that selects the vector entry
for the exception. The index, called the vector number, is an 8-bit value that is multiplied
by four to calculate an offset into the vector table. Of the 256 possible vector numbers, 64
are reserved by Freescale for definition by M68000 Family devices; the remaining 192 are
for definition by system designers.
MC68881/MC68882 USER'S MANUAL
FREESCALE
6-3
To Next Page
Loading...