6
The MPU can write to the condition CIR of the MC68882 when both the CU and APU are
busy. If exceptions are enabled and if each of the instructions report an exception, the
MC68882 reports the exceptions and executes the handlers, one at a time. The MC68882
restarts the conditional instruction after returning from each exception handler; that is, the
MC68882 restarts the instruction twice. It is important to note that the coprocessor com-
pletes all previous instructions and the MPU completes any executing exception handler
before the conditional instruction checks for a BSUN exception, evaluates the conditional
predicate, and reports the result to the MPU.
The FPCP detects a BSUN exception if the conditional predicate is one of the IEEE nonaware
branches,
and the NAN condition code bit is set. When the FPCP detects this exception, it
sets the BSUN bit in the FPSR exception status byte.
Trap
Disabled Results:
The FPCP evaluates the condition and reports the result to the MPU
in the response CIR.
Trap Enabled Results:
The FPCP reports a pre-instruction exception to the MPU with the
BSUN vector number instead of a true or false indication.
The BSUN exception is unique in that the trap is taken before the conditional predicate is
evaluated. Furthermore, the instruction that caused the BSUN exception is re-executed
following return from the BSUN trap handler. Therefore, it is the responsibility of the trap
handler to prevent the conditional instruction from taking the BSUN trap again. Four ways
are available to prevent taking the trap again.
The first way involves incrementing the stored program counter in the stack to bypass the
conditional instruction. This technique applies to situations where a fall-through is desired.
Be aware that accurate calculation of the program counter increment requires detailed
knowledge of the size of the conditional instruction being bypassed.
The second method is to clear the NAN bit of the FPSR condition code byte. However, this
alone cannot deterministically control the result indication (true or false) which would be
returned when the conditional instruction re-executes.
The third method is to disable the BSUN trap. Like the second method, this method cannot
control the result indication (true or false) which would be returned when the conditional
instruction re-executes.
The fourth method involves examining the condition predicate and setting the condition
code in the FPSR accordingly. This technique gives the most control since it is possible to
pre-determine the direction of program flow. Bit 7 of the F-line operation word indicates
where the conditional predicate is located. If bit 7 is set, the conditional predicate is the
lower six bits of the F-line operation word. Otherwise, the conditional predicate is the lower
six bits of the instruction word, which immediately follows the F-line operation word. Using
the conditional predicate and the table in 4.4.1 IEEE NonAware Tests, the condition codes
can be set to return a known result indication when the conditional instruction is re-
executed.
6.1.2 Signaling Not-a-Number
An SNAN is used as an escape mechanism for a user defined, non-lEEE data type. The
FPCP never creates an SNAN as a result of an operation; a NAN created by an operand
error exception is always a nonsignaling NAN.
FREESCALE
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MC68881/MC68882 USER'S MANUAL
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