When an SNAN is an operand involved in an arithmetic instruction, the SNAN bit is set in
the FPSR exception byte. Since the FMOVEM, FMOVE FPcr, and FSAVE instructions do not
modify the status bits, they cannot generate exceptions. Therefore, these instructions are
useful for manipulating SNANs.
Trap
Disabled Results:
If the destination data format is S, D, X, or P, then the SNAN bit in
the NAN is set to one and the resulting nonsignaling NAN is transferred to the destination.
No bits other than the SNAN bit of the NAN are modified, although the input NAN is
truncated if necessary. If the destination data format is B, W, or L, then the 8, 16, or 32
most significant bits of the SNAN significand, with the SNAN bit set, are written to the
destination.
Trap
Enabled Results:
For memory or MPU data register destinations, the result is written
in the same manner as if the trap were disabled, and then a mid-instruction exception is
signaled. If desired, the trap handler can overwrite the result.
For floating-point data register destinations, instruction execution is terminated, and the
floating-point data registers are not modified. In this case, the SNAN trap handler should
supply the result.
Note that the trap handler should use only the FMOVEM instruction to read or write the
floating-point data registers, since FMOVEM cannot generate further exceptions. Also, only
an FMOVEM instruction can write a SNAN into a floating-point data register.
6.1.30perand Error
The operand error category encompasses problems arising in a variety of operations, and
includes those errors not frequent or important enough to merit a specific exception con-
dition. Basically, an operand error occurs when an operation has no mathematical inter-
pretation for the given operands. The possible operand errors are listed in Table 6-2. When
an operand error occurs, the OPERR bit is set in the FPSR exception status byte.
Trap Disabled Results:
For a memory or MPU data register destination, several possible
results can be supplied, depending on the destination size and error type. (An operand
error is never generated when the destination is an MPU data register or memory and the
destination format is S, D, or X.)
If the operand error is caused by an integer overflow or if the floating-point data register
to be stored contains infinity, the result is the largest positive or negative integer that can
fit in the specified destination format size. If the destination is B, W, or L and the floating-
point number to be stored is a NAN, then the 8, 16, or 32 most significant bits of the NAN
significand are stored as the result.
For packed decimal results, if the k factor is greater than +17, the result returned is a
packed decimal string that assumes a k factor equal to +17. For packed decimal results
where the absolute value of the exponent is greater than 999, the decimal string is returned
with the three least significant exponent digits in EXP2, EXP1, and EXP0. The fourth digit,
EXP3, is supplied in the most significant four bits of the third byte in the string. Refer to
3.6 DATA FORMAT DETAILS for the packed decimal string format.
If the destination is a floating-point data register, an extended precision nonsignaling NAN
(with all ones mantissa) is stored in the destination floating-point data register.
MC68881/MC68882 USER'S MANUAL FREESCALE
6-7
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